Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

Abstract: A memory cell for use within a memory array includes a memory circuit and a read circuit. The memory circuit includes a non-volatile memory element (for example, a floating gate transistor) coupled to an RS flip flop. The RS flip flop is configured with a p-channel transistor coupled to receive a first enable signal and an n-channel transistor coupled to receive a second enable signal. The assertion of the enable signals is offset in time to control operations for forcing latch nodes to a specific voltage and enabling latching operation. The read circuit includes latch circuit coupled to outputs of the RS flip flop and operable as a sense amplifier circuit. The memory and read circuits are fabricated within a rectangular circuit area. Many such rectangular circuit area may be positioned adjacent to each other in a row or column of the memory array.

Abstract: A method is provided for managing the operation of a circuit operating in a slave mode. The circuit is connected to a bus having at least two of wires and a priority logic level. The slave circuit imposes the priority logic level on a first wire of the bus. While imposing, the slave circuit detects a possible conflict on the first wire resulting from a forcing, external to the slave circuit, of the first wire to another logic level. Upon detecting a conflict, the slave circuit is placed in a state stopping the sending by the circuit of any data over the bus while leaving the circuit listening to the bus.

Abstract: A method can be used for checking the operation of a device of electrically erasable programmable read-only memory type powered by a power supply voltage and associated with a power on reset circuit. The method includes implementation of at least one pilot operation corresponding to a phase of operation of the device that is identified as a phase that is inclined to malfunction in the event of a drop in the power supply voltage below a given value, execution of the at least one pilot operation during the operation of the memory device, and analysis of the result of the pilot operation so as to detect any malfunction not prevented by the reset circuit.

Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.

Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

Abstract: A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase.

Abstract: An electronic device includes at least one processing circuit connected through at least one terminal at a first reference voltage. At least one radio frequency communication circuit is connected at least to receive the reference voltage. At least one first pad is intended to be taken to a second reference voltage of at least one electronic circuit external to the device. At least one first resistive impedance is coupled between the terminal and the first pad.

Abstract: An electromagnetic transponder including a resonant circuit; a rectifying bridge having input terminals connected across the resonant circuit and having rectified output terminals providing an electronic circuit power supply voltage; and a device for limiting the voltage across the resonant circuit, connected between the input terminals of the rectifying bridge.

Abstract: Integrated non-volatile memory device includes an integrated memory cell of the EEPROM type with a floating-gate transistor and a selection transistor connected in series between a source line and a bit line, and a programming circuit for the memory cell. The selection transistor is connected between the floating-gate transistor and the source line. The programming circuit is configured for programming the t least one memory cell with a programming voltage split between a positive voltage and a negative voltage.

Abstract: A non-volatile memory device includes a matrix memory plane with columns of memory words respectively formed on each row of the memory plane by groups of memory cells and control elements respectively associated with the memory words of each row. At least some of the control elements associated with the memory words of the corresponding row form at least one control block of B control elements disposed next to one another, adjacent to a memory block containing the B memory words disposed next to one another and associated with these B control elements, a first electrically-conducting link connecting one of the B control elements to all the control electrodes of the state transistors of the corresponding group of memory cells and B-1 second electrically-conducting link(s) respectively connecting the B-1 control element(s) to all the control electrodes of the state transistors of the B-1 corresponding group(s) of memory cells.

Abstract: An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line. Each memory cell is formed by: a first select transistor with a first source-drain path; a second select transistor with a second source-drain path; a first floating gate transistor with a third source-drain path; and a second floating gate transistor with a fourth source-drain path. The first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line. The word line for each row of the memory is coupled to the gate terminals of the first and second select transistors. The control gate line for each row in coupled to the gate terminals of the first and second floating gate transistors.

Abstract: An EEPROM circuit includes a data reception register and a column decoder. A buffer memory having a size corresponding to the size of a data page is included between the data reception register and the column decoder.

Abstract: A method of programming an EEPROM, including: a first mode where a writing into cells is performed under a first voltage; and a second mode where the writing is performed under a second voltage smaller than the first one.

Abstract: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.

Abstract: A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.

Abstract: An electromagnetic transponder including a resonant circuit; a rectifying bridge having input terminals connected across the resonant circuit and having rectified output terminals providing an electronic circuit power supply voltage; and a device for limiting the voltage across the resonant circuit, connected between the input terminals of the rectifying bridge.

Abstract: A method for writing data into an EEPROM connected to an I2C bus, wherein the data to be written is transmitted in frames having a size corresponding to the size of a physical half-page of the memory. The programming of a data page in the memory is performed while another page is being received.

Abstract: A method for erasing a page-erasable EEPROM-type memory includes: the memory receiving a command associated with a set of addresses of pages of the memory to be erased, each page comprising several memory cell groups each forming a word, for each address of the set of addresses, selecting a word line corresponding to a page of the memory, and triggering the simultaneous erasing of all the selected word lines.

Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.