Patents by Inventor François Tailliet

François Tailliet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated Structure Comprising Neighboring Transistors
    Publication number: 20150270002
    Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.
    Type: Application
    Filed: March 13, 2015
    Publication date: September 24, 2015
    Inventors: Marc Battista, François Tailliet
  • Method for managing the operation of a memory device having a SRAM memory plane and a non volatile memory plane, and corresponding memory device
    Patent number: 9123413
    Abstract: A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: September 1, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • EEPROM PROGRAMMING
    Publication number: 20150243361
    Abstract: A method of programming an EEPROM, including: a first mode where a writing into cells is performed under a first voltage; and a second mode where the writing is performed under a second voltage smaller than the first one.
    Type: Application
    Filed: February 26, 2015
    Publication date: August 27, 2015
    Inventor: Francois Tailliet
  • Method for writing in an EEPROM-type memory including a memory cell refresh
    Patent number: 9099186
    Abstract: The present disclosure relates to a method for writing in an EEPROM memory, the method comprising steps of: storing the bits of a word to be written in first memory units, erasing a word to be modified, formed by first memory cells connected to a word line and first bit lines, reading bits stored in the memory cells of a word line WL<i>, in a first read mode and storing the bits read in second memory units, reading in a second read mode the bits stored in the memory cells of the word line, and programming each memory cell of the word line connected to a memory unit storing a bit in the programmed state of the word to be written, of an erased word or of a word comprising a bit having different states in the first and second read modes.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: August 4, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Method for Writing into and Reading a Multi-Levels EEPROM and Corresponding Memory Device
    Publication number: 20150117116
    Abstract: During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is controlled by the level of the control voltage applied to the control gate and the item of data is de facto written with the numerical value during the putting into conduction of the cell. The programming is then stopped.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 30, 2015
    Inventor: François Tailliet
  • SECURE MEMORY WHICH REDUCES DEGRADATION OF DATA
    Publication number: 20150109861
    Abstract: A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase.
    Type: Application
    Filed: December 29, 2014
    Publication date: April 23, 2015
    Inventor: Francois Tailliet
  • Method for processing a non-volatile memory, in particular a memory of the EEPROM type, for the storage then the extraction of information, and corresponding memory device
    Patent number: 9003265
    Abstract: Method for processing a non-volatile memory designed to store words containing data bits and control bits allowing an error correction with an error correction code, the method comprising the storage of information in the memory plane comprising an operation for writing in the memory plane at least one digital word modified with respect to at least one initial digital word not having any erroneous bit, said at least one modified digital word containing a bit having a modified value with respect to the value of this bit in said at least one initial digital word, the other bits of the modified digital word having values identical to those of these same bits in the initial digital word, the position of the modified bit in said at least one modified digital word defining the value of the digital information.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Method of burn-in test of EEPROM or flash memories
    Patent number: 9001602
    Abstract: A method for testing an integrated circuit includes, in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected to a first test voltage, and blocked high voltage MOS transistors of the integrated circuit are subjected to a second test voltage. The first test voltage is set to a value higher than a high supply voltage supplied to the high voltage MOS transistors in a normal operating mode, to make the gate oxides of transistors considered as insufficiently robust break down. The second test voltage is set to a value lower than the first test voltage and which can be supported by the blocked transistors, the states of the transistors being changed between the two steps.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Method of evaluating a semiconductor wafer dicing process
    Patent number: 8994022
    Abstract: Embodiments of the disclosure relate to a method of evaluating a semiconductor wafer dicing process, comprising providing evaluation lines extending in at least one scribe line of the wafer, dicing the wafer in the scribe line, evaluating the length of the evaluation lines, providing an information about their length, and using the information to evaluate the dicing process.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 31, 2015
    Assignee: STMicroelectronics Rousset SAS
    Inventor: Francois Tailliet
  • Secure memory which reduces degradation of data
    Patent number: 8964471
    Abstract: A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: February 24, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • COMMUNICATION ON AN I2C BUS
    Publication number: 20150046627
    Abstract: A communication system includes an I2C bus interconnecting at least one first device and one second device. At least one direct data link, other than the I2C bus, interconnects the first and second devices. The system is configurable to operate in: a first operating mode providing for data only transmission between the first and second devices over the I2C bus; and a second operating mode providing for simultaneous data transmission between the first and second devices over both the I2C bus and said data link.
    Type: Application
    Filed: August 6, 2014
    Publication date: February 12, 2015
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francois Tailliet
  • Transmission over an 12C bus
    Patent number: 8948209
    Abstract: A method and a system of multichannel transmission over a twin-wire bus including a data signal and a synchronization signal, data of a first channel being transmitted by a state coding of the data signal for a time period containing a first state of the synchronization signal, data of a second channel being transmitted by pulse coding outside of said period.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: February 3, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Conversion of a single-wire bus communication protocol
    Patent number: 8943254
    Abstract: A method of transmission-reception over a serial bus placed, when idle, in a first state at a first voltage, including: a transmit circuit capable of coding a transmission according to a first protocol in which the respective states of the bits are conditioned by time periods of fixed levels, indifferently in the first state or in a second state at a second voltage smaller than the first one; a receive circuit capable of interpreting a communication according to the first protocol; and a protocol converter, interposed between the bus and the transmit and receive circuits, to convert the signals to be transmitted to a second protocol in which the respective states of the bits are conditioned by respective time periods of fixed levels in the first state, and to convert the received signals from the second protocol to the first protocol.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: January 27, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Method for Managing the Operation of a Memory Device Having a SRAM Memory Plane and a Non Volatile Memory Plane, and Corresponding Memory Device
    Publication number: 20150016188
    Abstract: A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value.
    Type: Application
    Filed: June 26, 2014
    Publication date: January 15, 2015
    Inventors: François Tailliet, Marc Battista
  • Memory Device Including a SRAM Memory Plane and a Non Volatile Memory Plane, and Operating Methods
    Publication number: 20140369120
    Abstract: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 18, 2014
    Inventors: François Tailliet, Marc Battista
  • Compact Memory Device including a SRAM Memory Plane and a Non Volatile Memory Plane, and Operating Methods
    Publication number: 20140369119
    Abstract: A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 18, 2014
    Inventors: François Tailliet, Marc Battista
  • METHOD FOR BLOCK-ERASING A PAGE-ERASABLE EEPROM-TYPE MEMORY
    Publication number: 20140362640
    Abstract: A method for erasing a page-erasable EEPROM-type memory includes: the memory receiving a command associated with a set of addresses of pages of the memory to be erased, each page comprising several memory cell groups each forming a word, for each address of the set of addresses, selecting a word line corresponding to a page of the memory, and triggering the simultaneous erasing of all the selected word lines.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 11, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • METHOD FOR WRITING IN AN EEPROM-TYPE MEMORY INCLUDING A MEMORY CELL REFRESH
    Publication number: 20140355357
    Abstract: The present disclosure relates to a method for writing in an EEPROM memory, the method comprising steps of: storing the bits of a word to be written in first memory units, erasing a word to be modified, formed by first memory cells connected to a word line and first bit lines, reading bits stored in the memory cells of a word line WL<i>, in a first read mode and storing the bits read in second memory units, reading in a second read mode the bits stored in the memory cells of the word line, and programming each memory cell of the word line connected to a memory unit storing a bit in the programmed state of the word to be written, of an erased word or of a word comprising a bit having different states in the first and second read modes.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 4, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • MECHANISM FOR WRITING INTO AN EEPROM ON AN I2C BUS
    Publication number: 20140351489
    Abstract: A method for writing data into an EEPROM connected to an I2C bus, wherein the data to be written is transmitted in frames having a size corresponding to the size of a physical half-page of the memory. The programming of a data page in the memory is performed while another page is being received.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 27, 2014
    Inventor: François Tailliet
  • WRITING INTO AN EEPROM ON AN I2C BUS
    Publication number: 20140347931
    Abstract: An EEPROM circuit includes a data reception register and a column decoder. A buffer memory having a size corresponding to the size of a data page is included between the data reception register and the column decoder.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet