Patents by Inventor Francky Catthoor
Francky Catthoor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200089829Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.Type: ApplicationFiled: July 25, 2019Publication date: March 19, 2020Inventors: Pieter Weckx, Dmitrios Rodopoulos, Benjamin Kaczer, Francky Catthoor
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Patent number: 10592430Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.Type: GrantFiled: October 6, 2017Date of Patent: March 17, 2020Assignees: Imec vzw, Stitching Imec Nederland, Universidad Complutense de MadridInventors: Francky Catthoor, Matthias Hartmann, Jose Ignacio Gomez, Christian Tenllado, Sotiris Xydis, Javier Setoain Rodrigo, Thomas Papastergiou, Christos Baloukas, Anup Kumar Das, Dimitrios Soudris
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Publication number: 20190370914Abstract: A computer-implemented method and related device are disclosed for determining a plurality of operating scenarios of an energy system. The method comprises obtaining a plurality of performance measures of the energy system as a function of time corresponding to a plurality of sets of values of input variables. The method comprises clustering the plurality of sets of values of the input variables and the performance measures associated therewith into groups and defining a descriptor for each of the groups. The method also comprises outputting the descriptors of the groups for use in an online prediction or offline estimation of the energy system.Type: ApplicationFiled: May 30, 2019Publication date: December 5, 2019Inventors: Dimitrios Anagnostos, Francky Catthoor, Johannes Goverde
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Patent number: 10386878Abstract: A PV module is described with an array of PV cells whereby the module is reconfigurable, allowing different configurations to be applied after installation and during operation, i.e. at run-time. The run time configuration of the module has controllable devices. The main controllable devices are any of (individually or in combination): a) switches which determine the parallel/series connections of the cells as well as hybrid cases also. b) switches between the cells and local dc/dc converters and/or among the DC/DC converters; c) actively controlled bypass diodes placed in order to allow excess current to flow in the occurrence of a mismatch.Type: GrantFiled: October 5, 2012Date of Patent: August 20, 2019Assignee: IMEC VZWInventors: Francky Catthoor, Maria-Iro Baka
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Publication number: 20190197203Abstract: A method for generating/updating a database of current-voltage characteristic curves is disclosed. This method includes simulating for at least one combination of a topology of a photovoltaic cell group, an internal cell temperature(s) and a cell irradiation(s), a model of the photovoltaic cell group to provide a representative current-voltage characteristic curve, and clustering the current-voltage characteristic curves to identify at least one plurality of similar current-voltage characteristic curves.Type: ApplicationFiled: December 10, 2018Publication date: June 27, 2019Inventors: Francky Catthoor, Maria-Iro Baka, Patrizio Manganiello
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Publication number: 20190064438Abstract: A plasmonic device comprising an odd number of at least three input waveguides and at least one output waveguide is disclosed. In one aspect, the waveguides are adapted for guiding a surface plasmon polariton wave and the input waveguides are connected to the output waveguide at a waveguide junction. The inserted SPP waves have a phase at the waveguide junction which is either a first phase or a second phase. The second phase is shifted over ? with regard to the first phase and a combined SPP wave at the waveguide junction has a resulting phase wherein the dimensions of the waveguides are such that for different combinations of phases of the inserted waves the combined waves are phase aligned.Type: ApplicationFiled: August 9, 2018Publication date: February 28, 2019Inventors: Odysseas Zografos, Francky Catthoor, Sourav Dutta, Azad Naeemi
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Publication number: 20190034111Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.Type: ApplicationFiled: July 5, 2018Publication date: January 31, 2019Inventors: Francky Catthoor, Praveen Raghavan, Daniele Garbin, Dimitrios Rodopoulos, Odysseas Zografos
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Patent number: 10192009Abstract: A method is provided for calculating a performance of a photovoltaic module comprising at least a first photovoltaic cell and a second photovoltaic cell. The method comprises calculating a heat flow between the first photovoltaic cell and the second photovoltaic cell using a first thermal equivalent circuit of the first photovoltaic cell and a second thermal equivalent circuit of the second photovoltaic cell, wherein at least one node of the first thermal equivalent circuit is connected to a corresponding node of the second thermal equivalent circuit by a thermal coupling resistance. The method may be used for calculating the influence of spatial and temporal variations in the operation conditions on the performance, such as the energy yield, of a photovoltaic module or a photovoltaic system.Type: GrantFiled: September 16, 2015Date of Patent: January 29, 2019Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Hans Goverde, Francky Catthoor, Vikas Dubey, Jef Poortmans, Christiaan Baert
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Patent number: 10102908Abstract: A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.Type: GrantFiled: February 15, 2018Date of Patent: October 16, 2018Assignee: IMECInventors: Francky Catthoor, Komalan Manu Perumkunnil, Stefan Cosemans
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Patent number: 10073802Abstract: The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P<N, and P of the M outputs, P<M, via paths of connected and activated segments of the segmented bus network. The segments are linked by segmentation switches. The N data input ports and the M data output ports are connected via stubs to a subset of the segmentation switches.Type: GrantFiled: August 29, 2016Date of Patent: September 11, 2018Assignees: IMEC VZW, Stichting IMEC NederlandInventors: Francky Catthoor, Praveen Raghavan
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Patent number: 10019361Abstract: The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.Type: GrantFiled: August 29, 2016Date of Patent: July 10, 2018Assignee: IMEC VZWInventors: Francky Catthoor, Praveen Raghavan, Matthias Hartmann, Komalan Manu Perumkunnil, Jose Ignacio Gomez, Christian Tenllado
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Publication number: 20180174653Abstract: A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: Francky Catthoor, Komalan Manu Perumkunnil, Stefan Cosemans
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Publication number: 20180101483Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.Type: ApplicationFiled: October 6, 2017Publication date: April 12, 2018Applicants: IMEC VZW, Stichting IMEC NederlandInventors: Francky Catthoor, Matthias Hartmann, Jose Ignacio Gomez, Christian Tenllado, Sotiris Xydis, Javier Setoain Rodrigo, Thomas Papastergiou, Christos Baloukas, Anup Kumar Das, Dimitrios Soudris
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Patent number: 9899086Abstract: A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.Type: GrantFiled: January 24, 2014Date of Patent: February 20, 2018Assignee: IMECInventors: Francky Catthoor, Komalan Manu Perumkunnil, Stefan Cosemans
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Patent number: 9632752Abstract: The present system and method relate to a system for performing a multiplication. The system is arranged for receiving a first data value, and comprises means for calculating at run time a set of instructions for performing a multiplication using the first data value, storage means for storing the set of instructions calculated at run time, multiplication means arranged for receiving a second data value and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data values using the at least one instruction.Type: GrantFiled: December 20, 2012Date of Patent: April 25, 2017Assignees: IMEC, Katholieke Universiteit Leuven, KU LEUVEN R&D, Samsung Electronics Co., Ltd.Inventors: Robert Fasthuber, Praveen Raghavan, Francky Catthoor
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Publication number: 20170091094Abstract: The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.Type: ApplicationFiled: August 29, 2016Publication date: March 30, 2017Applicant: IMEC VZWInventors: Francky Catthoor, Praveen Raghavan, Matthias Hartmann, Komalan Manu Perumkunnil, Jose Ignacio Gomez, Christian Tenllado
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Publication number: 20170083469Abstract: The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P<N, and P of the M outputs, P<M, via paths of connected and activated segments of the segmented bus network. The segments are linked by segmentation switches. The N data input ports and the M data output ports are connected via stubs to a subset of the segmentation switches.Type: ApplicationFiled: August 29, 2016Publication date: March 23, 2017Applicants: IMEC VZW, Stichting IMEC NederlandInventors: Francky Catthoor, Praveen Raghavan
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Publication number: 20170077869Abstract: The present disclosure relates to reconfigurable voltaic modules. One example embodiment includes a photovoltaic module. The photovoltaic module includes a plurality of photovoltaic cells arranged in a grid having logical rows and columns. The photovoltaic module also includes a plurality of non-reconfigurable interconnects electrically interconnecting subsets of the plurality of photovoltaic cells to form a plurality of cell strings. In addition, the photovoltaic module includes a plurality of reconfigurable interconnects. Each cell string includes at least four photovoltaic cells connected in an electrical series from a first cell to a last cell, the first cell and the last cell being located on a same edge of the grid.Type: ApplicationFiled: August 25, 2016Publication date: March 16, 2017Applicant: IMEC VZWInventors: Francky Catthoor, Maria-Iro Baka
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Publication number: 20160283629Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.Type: ApplicationFiled: March 25, 2016Publication date: September 29, 2016Inventors: Pieter Weckx, Dmitrios Rodopoulos, Benjamin Kaczer, Francky Catthoor
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Publication number: 20160179577Abstract: The present disclosure relates to a method of managing the operation of a digital synchronous electronic system with a guaranteed lifetime, using digital processing means. The method comprises: monitoring the electronic system at run time, while the electronic system executes a set of application tasks currently running on the electronic system in a current system working mode; detecting a violation in at least one parameter of the electronic system, the violation affecting one or more guaranteed objectives or one or more cost functions; selecting at least one condition to revise the current system working mode of the electronic system; and based on the at least one condition, selecting a revised system working mode to continue execution of the set of application tasks.Type: ApplicationFiled: December 18, 2015Publication date: June 23, 2016Applicant: Stichting IMEC NederlandInventors: Francky Catthoor, Dimitrios Rodopoulos, Dimitrios Soudris