Abstract: Disclosed is a method for managing the operation of a telecom system, and minimizing the energy to be drained from a power supply. According to the method, a rate constraint and telecom environment conditions are determined. Then, a working point is selected a plurality of predetermined working points based on the rate constraint and the telecom environment conditions. The telecom system is operated at the selected working point by setting corresponding control parameters.

Abstract: An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.

Abstract: A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

Abstract: A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line.

Abstract: Presented is a method of managing the operation of a system including a processing subsystem configured to run a multimedia application and a telecommunication subsystem. The method includes determining telecom environment conditions, and selecting a working point from a plurality of predetermined working points. The selecting is based at least in part on the determined environmental conditions. The method also includes setting control parameters in the multimedia application and/or the telecommunication subsystem to configure the system to operate at the selected working point, and operating the system at the selected working point.

Abstract: One aspect of the invention includes a method of address expression optimization of source-level code. The source-level code describes the functionality of an application to be executed on a digital device. The method comprises first inputting first source-level code that describes the functionality of the application into optimization system. The optimization system then transforms the first source-level into a second source level that has fewer nonlinear operations than the first source-level code.

Abstract: A method and device for converting first program code into second program code, such that the second program code has an improved execution on a targeted programmable platform, is disclosed. In one aspect, the method includes grouping operations on data for joint execution on a functional unit of the targeted platform, scheduling operations on data in time, and assigning operations to an appropriate functional unit of the targeted platform. Detailed word length information, rather than the typically used approximations like powers of two, may be used in at least one of the grouping, scheduling or assigning operations.

Abstract: A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.

Abstract: A microcomputer architecture comprises a microprocessor unit and a first memory unit, the microprocessor unit comprising a functional unit and at least one data register, the functional unit and the at least one data register being linked to a data bus internal to the microprocessor unit. The data register is a wide register comprising a plurality of second memory units which are capable to each contain one word. The wide register is adapted so that the second memory units are simultaneously accessible by the first memory unit, and so that at least part of the second memory units are separately accessible by the functional unit.

Abstract: A system and method for converting on a computer environment a first code into a second code to improve performance or lower energy consumption on a targeted programmable platform is disclosed. The codes represent an application. In one aspect, the method includes loading on the computer environment the first code and for at least part of the variables within the code the bit width required to have the precision and overflow behavior as demanded by the application. The method further includes converting the first code into the second code by grouping operations of the same type on the variables for joint execution on a functional unit of the targeted programmable platform, the grouping operations using the required bit width, wherein the functional unit supports one or more bit widths, the grouping operation being selected to use at least partially one of the supported bit widths.

Abstract: Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system as well as methods, apparatus and software products for run-time memory management techniques of such a system. Memory assignment techniques are described for assigning data to a hierarchical memory particularly for multi-tasked applications where data of dynamically created/deleted tasks is allocated at run-time. The energy consumption of hierarchical memories such as multi-banked memories depends largely on how data is assigned to the memory banks. Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system which improve a cost function such as energy consumption.

Abstract: The present invention provides a driver circuit for driving a line terminated by a load, wherein said driver circuit is configurable for design time selected energy/delay working points. The configuration capability is used, e.g. during run-time, for dynamically selecting a suitable energy/delay working point, given the circumstances wherein said driver circuit has to operate. The driver circuit is in particular targeted for on-chip communication, but is not limited thereto.

Abstract: A method and system for converting application code into optimized application code or into execution code suitable for execution on a computation engine with an architecture comprising at least a first and a second level of data memory units are disclosed. In one aspect, the method comprises obtaining application code, the application code comprising data transfer operations between the levels of memory units. The method further comprises converting at least a part of the application code. The converting of application code comprises scheduling of data transfer operations from a first level of memory units to a second level of memory units such that accesses of data accessed multiple times are brought closer together in time than in the original code.

Abstract: A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.

Abstract: One inventive aspect relates to a display system for displaying information and a method for displaying. The system comprises a processing unit and a display unit comprising a display panel. On the image data processing path for transferring information to the display panel the number of writable memory components external to the display panel is limited to one. The writable memory component is adapted to store at least a single image frame. The systems and methods allow to reduce the power consumption based on reduction of the number of memory accesses. In another inventive aspect, a method and system is provided wherein updating of pixel information is performed content dependent. In still another inventive aspect, a system is provided wherein the display panel is connected to the processing unit using a separate, dedicated display bus.

Abstract: A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.

Abstract: An aspect of the present invention provides a design environment in which a floorplan of a semiconductor device is optimised by taking into account activation or access frequency information to and from resources. Since segmented bus architecture is also a good alternative approach for the power consumption of the network, the floorplanning approach for energy optimization of the communicating network is adapted for such architectures in embodiments of the present invention. The provided method comprises both architecture optimizations as well as physical design optimizations.

Abstract: In one aspect, a method for managing a plurality of virtual links from at least two different sources shared on a physical communication line extending between a first unit and a second unit is disclosed. The method comprises establishing a first situation in which the total bit width of the communication line is at least partly occupied by a first group of virtual links. The method further comprises configuring a second situation in which a first portion of the total bit width is allocated to the first group of virtual links and a second portion of the total bit width is allocated to a second group of virtual links. The method further comprises switching from the first situation to the second situation. In another aspect, a digital network includes a control unit for managing the sharing of the plurality of virtual links on the physical communication line according to a predetermined switching granularity m, which is smaller than the bit width n of the input and output ports of the units.

Abstract: First several possible working points are stored with different mappings to available modules. Each of these working points involves different trade-offs for important criteria related to performance and costs. At the design stage, these trade-off points for the criteria are not calibrated to the actual run-time conditions. Subsequently, based on actual values of the leakage criteria caused by temperature variations and/or ageing at given run-time conditions for (a subset of) the working points, it is possible to calibrate the trade-off curves and use a run-time controller to select the most suited working points afterward for an actual circuit. These active working points are selected to just meet the necessary system requirements on performance, while minimizing any of the important cost parameters.

Abstract: The present invention relates to the design of essentially digital systems and components. In one embodiment, a parameterized model of a sub-component of an essentially digital system is provided. This sub-component is used in components of the system, e.g. interconnect at the different levels (up to the packaging level) and includes all relevant parameters with their physical constraints. If certain parameters do not play a significant role at the system level exploration, they can be left out of the exploration. But then they should preferably be fixed on the value that allows the cheapest and most reliable process technology solutions (independent of their delay or energy consequences). For the parameters that do have a large impact, the subranges of their trade-off curves, especially Pareto curves, that are appropriate for a given target domain (e.g. ambient multimedia) should be carefully selected to match design cost, process cost and reliability issues.