Abstract: A microcomputer architecture comprises a microprocessor unit and a first memory unit, the microprocessor unit comprising a functional unit and at least one data register, the functional unit and the at least one data register being linked to a data bus internal to the microprocessor unit. The data register is a wide register comprising a plurality of second memory units which are capable to each contain one word. The wide register is adapted so that the second memory units are simultaneously accessible by the first memory unit, and so that at least part of the second memory units are separately accessible by the functional unit.

Abstract: Presented is a method of managing the operation of a system including a processing subsystem configured to run a multimedia application and a telecommunication subsystem. The method includes determining telecom environment conditions, and selecting a working point from a plurality of predetermined working points. The selecting is based at least in part on the determined environmental conditions. The method also includes setting control parameters in the multimedia application and/or the telecommunication subsystem to configure the system to operate at the selected working point, and operating the system at the selected working point.

Abstract: One aspect of the invention includes a method of address expression optimization of source-level code. The source-level code describes the functionality of an application to be executed on a digital device. The method comprises first inputting first source-level code that describes the functionality of the application into optimization system. The optimization system then transforms the first source-level into a second source level that has fewer nonlinear operations than the first source-level code.

Abstract: Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system as well as methods, apparatus and software products for run-time memory management techniques of such a system. Memory assignment techniques are described for assigning data to a hierarchical memory particularly for multi-tasked applications where data of dynamically created/deleted tasks is allocated at run-time. The energy consumption of hierarchical memories such as multi-banked memories depends largely on how data is assigned to the memory banks. Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system which improve a cost function such as energy consumption.

Abstract: The present invention provides a driver circuit for driving a line terminated by a load, wherein said driver circuit is configurable for design time selected energy/delay working points. The configuration capability is used, e.g. during run-time, for dynamically selecting a suitable energy/delay working point, given the circumstances wherein said driver circuit has to operate. The driver circuit is in particular targeted for on-chip communication, but is not limited thereto.

Abstract: The invention presents video information stream encoding methods used in applications of a data storage and transfer design methodology for data-dominated applications. The invention relates to video encoding methods with variable video frames designed such that the digital system on which the methods are implemented, consumes a minimal of power, during their execution and still obtain excellent performance such as speed compliance. The resulting video information stream encoding methods can be mapped on different processor architectures and custom hardware. The methods enable combined low power consumption, reduced bus loading and increased performance to achieve speed compliance. The encoding methods are essentially based on block-based motion estimation and grouping of motion estimations of various video frames.

Abstract: Methods and apparatus are described in which, at design-time a thorough analysis and exploration is performed to represent a multi-objective “optimal” trade-off point or points, e.g. on Pareto curves, for the relevant cost (C) and constraint criteria. More formally, the trade-off points may e.g. be positions on a hyper-surface in an N-dimensional Pareto search space. The axes represent the relevant cost (C), quality cost (Q) and restriction (R) criteria. Each of these working points is determined by positions for the system operation (determined during the design-time mapping) for a selected set of decision knobs (e.g. the way data are organized in a memory hierarchy). The C-Q-R values are determined based on design-time models that then have to be “average-case” values in order to avoid a too worst-case characterisation. At processing time, first a run-time BIST manager performs a functional correctness test, i.e. checks all the modules based on stored self-test sequences and “equivalence checker” hardware.

Abstract: Disclosed is a method for managing the operation of a telecom system, and minimizing the energy to be drained from a power supply. According to the method, a rate constraint and telecom environment conditions are determined. Then, a working point is selected a plurality of predetermined working points based on the rate constraint and the telecom environment conditions. The telecom system is operated at the selected working point by setting corresponding control parameters.

Abstract: A system and method are provided that include determining optimum memory organization in an electronic device, wherein further determined are optimum resource interconnection patterns. One aspect of the system and method includes determining resource, e.g., memories and data paths, interconnection patterns of complex bus structures with switches using system-level information about the data-transfer conflicts. The quantity of memories within an electronic device, the size of the memories and the interconnection between the memories, including the interconnection of the memories with one or more data paths, defines a memory organization of an electronic device. Another aspect of the system and method relates to selecting an optimized memory organization, including selecting an optimized interconnection pattern between the memories and between the memories and the data paths.

Abstract: An aspect of the present invention provides a design environment in which a floorplan of a semiconductor device is optimised by taking into account activation or access frequency information to and from resources. Since segmented bus architecture is also a good alternative approach for the power consumption of the network, the floorplanning approach for energy optimization of the communicating network is adapted for such architectures in embodiments of the present invention. The provided method comprises both architecture optimizations as well as physical design optimizations.

Abstract: The present invention relates to the design of essentially digital systems and components. In one embodiment, a parameterized model of a sub-component of an essentially digital system is provided. This sub-component is used in components of the system, e.g. interconnect at the different levels (up to the packaging level) and includes all relevant parameters with their physical constraints. If certain parameters do not play a significant role at the system level exploration, they can be left out of the exploration. But then they should preferably be fixed on the value that allows the cheapest and most reliable process technology solutions (independent of their delay or energy consequences). For the parameters that do have a large impact, the subranges of their trade-off curves, especially Pareto curves, that are appropriate for a given target domain (e.g. ambient multimedia) should be carefully selected to match design cost, process cost and reliability issues.

Abstract: The invention presents video information stream encoding methods used in applications of a data storage and transfer design methodology for data-dominated applications. The invention relates to video encoding methods with variable video frames designed such that the digital system on which the methods are implemented, consumes a minimal of power, during their execution and still obtain excellent performance such as speed compliance. The resulting video information stream encoding methods can be mapped on different processor architectures and custom hardware. The methods enable combined low power consumption, reduced bus loading and increased performance to achieve speed compliance. The encoding methods are essentially based on block-based motion estimation and grouping of motion estimations of various video frames.

Abstract: A loop transformation step, to be performed on code and improving data transfer and storage, while executing said transformed code on a parallel processor, is disclosed. Improval of the data locality and regularity of the algorithm, described by said code, is aimed at. Said loop transformation step works globally and is feasible for realistic code sizes.

Abstract: Methods and architectures for turbo decoding are presented. The methods are such that low energy consumption is obtained with reduced memory requirements. Moreover the methods show improved performance with respect to latency.

Abstract: The invention presents video information stream encoding methods used in applications of a data storage and transfer design methodology for data-dominated applications. The invention relates to video encoding methods with variable video frames designed such that the digital system on which the methods are implemented, consumes a minimal of power, during their execution and still obtain excellent performance such as speed compliance. The resulting video information stream encoding methods can be mapped on different processor architectures and custom hardware. The methods enable combined low power consumption, reduced bus loading and increased performance to achieve speed compliance. The encoding methods are essentially based on block-based motion estimation and grouping of motion estimations of various video frames.

Abstract: A formalized method for part of the design decisions, related to memory, involved while designing an essentially digital device is presented. The method shows how to traverse through and how to limit the search space being examined while solving these memory related design decisions. The method focuses on power consumption of said essentially digital device. A method for determining an optimized memory organization of an essentially digital device, wherein data reuse possibilities are explored, is described.

Abstract: Methods and architectures for turbo decoding are presented. The methods are such that low energy consumption is obtained with reduced memory requirements. Moreover the methods show improved performance with respect to latency.

Abstract: The power consumption, memory allocation, and CPU time used in a signal processor executing a fast transform can be optimized by using a particular method of scheduling the calculations. The transform typically is used to transform a first m-dimensional indexed array into a second m-dimensional indexed array. The elements of the first m-dimensional array are grouped according to the index difference between the elements of the particular butterfly code of that stage. A second grouping of elements is composed of butterfly code elements having non-maximal index differences. The second group advantageously includes elements also assigned to the first group. The butterfly codes of the groups are arranged sequentially and are executed in the sequential schedule. In a second embodiment, elements are grouped according to a group specific threshold value. Memory is allocated to the groups according to the size of the group such that the access to memory is minimized during execution.

Abstract: Methods and architectures for turbo decoding are presented. The methods are such that low energy consumption is obtained with reduced memory requirements. Moreover the methods show improved performance with respect to latency.

Abstract: The present invention proposes effective solutions for the design of Virtual Memory Management for applications with dynamic data types in an embedded (HW or SW) processor context. A structured search space for VMM mechanisms with orthogonal decision trees is presented. Based on said representation a systematic power exploration methodology is proposed that takes into account characteristics of the applications to prune the search space and guide the choices of a VMM for data dominated applications. A parameterizable model, called Flexible Pools, is proposed. This model limits the exploration of the Virtual Memory organization considerably without limiting the optimization possibilities.