Abstract: A memory device is described that enhances initialization of the memory device. In the prior art, initialization of synchronous Flash memory requires the release of hardware signal line, RP#, or an initialization command, LCR, and a following initialization time wait period of 50 ?S to 100 ?S. The improved memory device of the detailed invention begins initialization of internal values upon acquiring stable power. The initialization cycle of the detailed memory loops and continues until a command is received from the host controller and is immediately available for access. This allows the utilization of the detailed memory in systems wherein the host controller cannot supply an initializing signal (RP# or LCR). The detailed memory also allows for immediate availability of the memory upon issuance of the command allowing for a fast first access.

Abstract: An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate other integrated circuit devices. The integrated circuit register can also be reset to reflect the original manufacturer information. The integrated circuit can be a memory device and allows the user to upgrade a system while indicating to the original system that the device is compatible.

Abstract: A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or tri-state, depending upon the data read from the array. Output drivers of the memory are placed in a tri-state condition in response to a detected read error. Non-compressed internal I/O lines are used during testing to provide control signals to the driver circuitry to selectively place drivers in the tri-state mode. Once a tri-state is detected four columns of memory cells can be replaced with four columns of redundant memory cells without requiring additional non-compressed testing.

Abstract: A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has risen substantially to a supply voltage without draining the pumped voltage.

Abstract: Power consumption by a memory device may be controlled by maintaining data input buffers in an off state until a command sequence containing a specified command is received by the memory. A software command sequence is provided to the memory device where the software command sequence was constructed by generating a command sequence including the specified command. The data input buffers are returned to an off state upon completion of a memory operation defined in the received command sequence.

Abstract: A non-volatile memory device includes a memory array having erasable blocks or memory cells. The array has pages that are not one continuous array row. As such, the array row is segmented into page rows. The page rows are addressed contiguously across the page and a main erase block is divided into sub-erase blocks that follow the page row segmentation.

Abstract: A memory device includes memory cells arranged in multiple blocks. A register is provided to track multiple open pages per block of the memory. In one embodiment, the register is located in the memory device and used to determine if a memory access is to be performed. In another embodiment, the register is located external to the memory and used by a processor and/or chip set to determine if an access request is needed.

Abstract: Power consumption by a memory device is optimized by maintaining data input buffers in an off state until a command sequence containing a write command is received by the memory. A command sequence is provided to the memory device where the command sequence was constructed by generating a command sequence of n cycles and providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, where m is less than n. The data input buffers are returned to an off state upon completion of a program or erase operation defined in the received command sequence.

Abstract: A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.

Abstract: A method and apparatus for discharging global bitlines in a flash memory to a voltage sufficiently low to avoid drain disturb for non-selected cells in a programming operation. A discharge device allows discharge of global bitlines coupled to local bitlines before a programming operation.

Abstract: A method of erasing a memory cell includes the step of erasing a memory cell. The current in the memory cell is measured. If the measured memory cell current approximately exceeds a predetermined level, the memory cell is soft programmed so if the memory cell is not overerased, the memory cell is undisturbed. The memory cell is soft programmed until the measured memory cell current is less than or equal to the predetermined level.

Abstract: A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without increasing the line-to-line capacitance. The capacitances, resistances, and RC time constants can be optimized for a single line of a group or for the entire group of interconnect lines, providing a low average value or a uniform value across all lines for uniform propagation delay.

Abstract: A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has risen substantially to a supply voltage without draining the pumped voltage.

Abstract: A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates pumps in response to a count output of the counter. In one embodiment, the pump output current is increased as the counter output increases. The memory allows for erase operations that reduce leakage current during initiation of an erase operation.

Abstract: A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or tri-state, depending upon the data read from the array. Output drivers of the memory are placed in a tri-state condition in response to a detected read error. Non-compressed internal I/O lines are used during testing to provide control signals to the driver circuitry to selectively place drivers in the tri-state mode. Once a tri-state is detected four columns of memory cells can be replaced with four columns of redundant memory cells without requiring additional non-compressed testing.

Abstract: An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate other integrated circuit devices. The integrated circuit register can also be reset to reflect the original manufacturer information. The integrated circuit can be a memory device and allows the user to upgrade a system while indicating to the original system that the device is compatible.

Abstract: An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test operations to receive elevated supply voltages. The reset connection is coupled to a bias circuit to maintain an inactive state such that the integrated circuit is not reset during the test operation when the reset connection is not actively driven by the external supply.

Abstract: An improved Flash memory device with a synchronous interface has been detailed that enhances initialization of the Flash memory device. In the prior art, initialization of synchronous Flash memory requires the release of hardware signal line, RP#, or an initialization command, LCR, and a following initialization time wait period of 50 ?S to 100 ?S. The improved Flash memory device of the detailed invention begins initialization of internal values upon acquiring stable power. The initialization cycle of the detailed synchronous Flash memory loops and continues until a “STOP” command is received from the host controller and is immediately available for access. This allows the utilization of the detailed synchronous Flash memory in systems wherein the host controller cannot supply an initializing signal (RP# or LCR). The detailed synchronous Flash memory also allows for immediate availability of the Flash memory upon issuance of the “STOP” command allowing for a fast first access.

Abstract: A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without increasing the line-to-line capacitance. The capacitances, resistances, and RC time constants can be optimized for a single line of a group or for the entire group of interconnect lines, providing a low average value or a uniform value across all lines for uniform propagation delay.

Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows the memory to have an efficient Flash internal structure, while logically re-mapping this architecture externally to a compatible virtual SDRAM architecture. This allows for access and operation of the improved memory device with a compatible SDRAM controller device, while Flash specific functions can be performed with an SDRAM command sequence. Internal to the memory, memory array banks are divided into four equal segments by row range and logically re-mapped by placing the segments virtually beside each other. This forms a virtual memory bank structure of equivalent rows and columns as a comparable SDRAM device. Additionally, the improved memory device may also have an extended interface that allows for direct access to the internal Flash memory architecture without logical abstraction.