Abstract: A flash memory has been described that has an interface corresponding to a rambus dynamic random access memory (RDRAM). The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the falling edge of the clock signal.

Abstract: A flash memory has been described that has an interface corresponding to a rambus dynamic random access memory (RDRAM). The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the falling edge of the clock signal.

Abstract: A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates pumps in response to a count output of the counter. In one embodiment, the pump output current is increased as the counter output increases. The memory allows for erase operations that reduce leakage current during initiation of an erase operation.

Abstract: A memory device is provided. The memory device has a memory array and control circuitry to control operations to the memory array. A redundant register having a bit is also included. The bit is at a first level when two rows of the memory array are shorted together or at a second level when four rows of the memory array are shorted together. The control circuitry instructs an address counter, during an erase operation, to increment row addresses of the rows of the memory array by two rows when the bit is at the first level or four rows when the bit is at the second level.

Abstract: A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a writer enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.

Abstract: An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test operations to receive elevated supply voltages. The reset connection is coupled to a bias circuit to maintain an inactive state such that the integrated circuit is not reset during the test operation when the reset connection is not actively driven by the external supply.

Abstract: A synchronous memory device includes an array of memory cells. During a read operation data from a row of the array is stored in a latch circuit and randomly read. The memory device can be placed in a low power consumption mode where a voltage pump circuit used to provide an access voltage is powered down. The time required to restart the voltage pump typically limits the speed in which data in the array can be read following a low power mode. The memory device maintains power to the latch circuit during the low power mode such that the latched data can be read following a low power mode without waiting for the pump circuit to reach a stable output voltage level.

Abstract: A flash memory has been described that has an interface corresponding to a rambus dynamic random access memory (RDRAM). The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the falling edge of the clock signal.

Abstract: A transition of an external enable signal generates a reset pulse to a counter to set the counter into a known state. The counter, clocked by the external clock signal, generates a clock signal that is decoded by a fuse decoder circuit. The fuse decoder circuit outputs a selection signal to a trim circuit. The trim circuit produces a voltage selection signal, such as a resistance value, that is indicated by the selection signal for use by an internal reference voltage generation circuit. The output of the internal reference voltage generation circuit is compared to the external reference voltage. The counter circuit continues counting until the internal reference voltage is equal to or greater than the external reference voltage. The counter is disabled and the final count that produced the proper internal reference voltage is stored in non-volatile memory cells for future use.

Abstract: A transition of an external enable signal generates a reset pulse to a counter to set the counter into a known state. The counter, clocked by the external clock signal, generates a clock signal that is decoded by a fuse decoder circuit. The fuse decoder circuit outputs a selection signal to a trim circuit. The trim circuit produces a voltage selection signal, such as a resistance value, that is indicated by the selection signal for use by an internal reference voltage generation circuit. The output of the internal reference voltage generation circuit is compared to the external reference voltage. The counter circuit continues counting until the internal reference voltage is equal to or greater than the external reference voltage. The counter is disabled and the final count that produced the proper internal reference voltage is stored in non-volatile memory cells for future use.

Abstract: An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test operations to receive elevated supply voltages. The reset connection is coupled to a bias circuit to maintain an inactive state such that the integrated circuit is not reset during the test operation when the reset connection is not actively driven by the external supply.

Abstract: A flash memory has erase blocks aligned primarily with array rows and secondarily with array rows. This architecture allows data to be stored across numerous pages without risking accidental erasure caused by crossing multiple erase blocks. As a result, non-volatile memory devices to be more easily substituted for volatile memory devices. In one embodiment, a flash memory includes an array of memory cells that have a plurality of adjacent pages. Addresses of the memory cells are scrambled within the pages to define erase blocks that cross the page boundaries.

Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SCRAM compatible interface. The memory device employs a virtual paging scheme that allows for the architecture of the memory to implement an efficient Flash memory structure internally. Externally, the memory logically maps the internal Flash architecture to an SCRAM compatible interface and virtual architecture, allowing for memory access and operation with a compatible SCRAM controller device. A double data rate interface is provided to allow data to be input and output from the memory in synchronization with both rising and falling edges of a clock signal.

Abstract: A memory device is provided. The memory device has a memory array and control circuitry to control operations to the memory array. A redundant register having a bit is also included. The bit is at a first level when two rows of the memory array are shorted together or at a second level when four rows of the memory array are shorted together. The control circuitry instructs an address counter, during an erase operation, to increment row addresses of the rows of the memory array by two rows when the bit is at the first level or four rows when the bit is at the second level.

Abstract: A memory and system reduce power consumption by reducing a power supply level. The memory includes input circuitry coupled to a data communication bus. The input circuitry has first and second threshold detection levels to detect voltage transitions of data signals communicated on the bus. The memory device changes threshold voltage detection levels in synchronization with other memories coupled to the bus. In one embodiment, the synchronization is performed while the memory devices are in a power down state. A power supply provided to the memory device is changed while the memory is in the power-down state.

Abstract: A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or tri-state, depending upon the data read from the array. Output drivers of the memory are placed in a tri-state condition in response to a detected read error. Non-compressed internal I/O lines are used during testing to provide control signals to the driver circuitry to selectively place drivers in the tri-state mode. Once a tri-state is detected four columns of memory cells can be replaced with four columns of redundant memory cells without requiring additional non-compressed testing.

Abstract: A non-volatile memory device includes a memory array having erasable blocks or memory cells. The array has pages that are not one continuous array row. As such, the array row is segmented into page rows. The page rows are addressed contiguously across the page and a main erase block is divided into sub-erase blocks that follow the page row segmentation.

Abstract: A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has risen substantially to a supply voltage without draining the pumped voltage.

Abstract: A synchronous memory device includes an array of memory cells. During a read operation data from a row of the array is stored in a latch circuit and randomly read. The memory device can be placed in a low power consumption mode where a voltage pump circuit used to provide an access voltage is powered down. The time required to restart the voltage pump typically limits the speed in which data in the array can be read following a low power mode. The memory device maintains power to the latch circuit during the low power mode such that the latched data can be read following a low power mode without waiting for the pump circuit to reach a stable output voltage level.

Abstract: A method and apparatus for discharging global bitlines in a flash memory to a voltage sufficiently low to avoid drain disturb for non-selected cells in a programming operation. A discharge device allows discharge of global bitlines coupled to local bitlines before a programming operation.