Patents by Inventor Frederic Boutaud
Frederic Boutaud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20050278512Abstract: A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.Type: ApplicationFiled: April 26, 2005Publication date: December 15, 2005Inventors: Peter Ehlig, Frederic Boutaud, James Hollander
-
Publication number: 20050251638Abstract: A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.Type: ApplicationFiled: December 21, 2004Publication date: November 10, 2005Inventors: Frederic Boutaud, Peter Ehlig
-
Patent number: 6918025Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: January 6, 2003Date of Patent: July 12, 2005Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
-
Patent number: 6907538Abstract: Described is a system and method for centralized synchronization for the transportation of data between devices in different clock domains. In a preferred embodiment, synchronization logic synchronizes read data from an asynchronous peripheral to a bus clock. Rather than being located on each peripheral, the synchronization logic is located in the bus interface logic. When there is an indication that synchronization is needed for a peripheral, the synchronization logic samples the data bus twice or more and compares the values of consecutive data samples. If the data samples are equal, this data is returned to the bus master. If they are different, the data in the next cycle is returned to the bus master.Type: GrantFiled: October 16, 2001Date of Patent: June 14, 2005Assignee: Analog Devices, Inc.Inventor: Frederic Boutaud
-
Publication number: 20050108505Abstract: A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code discontinuity is encountered, the unified memory is accessed a first time during an instruction cycle with a dummy access. The unified memory is accessed a second time during the instruction cycle when a program code discontinuity is encountered with either a data access, as in the case of a last instruction of a loop, or an instruction access, as in the case of a jump instruction.Type: ApplicationFiled: November 17, 2003Publication date: May 19, 2005Inventor: Frederic Boutaud
-
Publication number: 20040204003Abstract: The present invention is directed to methods and apparatus which may be used to help prevent electronic devices such as, for example, cell phones from operating with software copied from (and only authorized for use by) another device. The present invention is also directed to devices such as, for example, cell phones, that employ any of such methods and apparatus.Type: ApplicationFiled: July 31, 2002Publication date: October 14, 2004Inventors: Joern Soerensen, Palle Birk, Frederic Boutaud
-
Patent number: 6732235Abstract: A digital signal processing system includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masters each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.Type: GrantFiled: November 6, 2000Date of Patent: May 4, 2004Assignee: Analog Devices, Inc.Inventors: Paul D. Krivacek, Jørn Sørensen, Frederic Boutaud
-
Publication number: 20030226002Abstract: A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.Type: ApplicationFiled: January 6, 2003Publication date: December 4, 2003Inventors: Frederic Boutaud, Peter N. Ehlig
-
Patent number: 6624678Abstract: Described is a Schmitt trigger cell that can be disabled under conditions of unknown gate voltages (e.g., floating or toggling input) such that the core is isolated from the Schmitt trigger input. This is accomplished by circuitry that disables current flow through those transistors whose gate voltages are unknown during such conditions and that forces a known output onto the output terminal.Type: GrantFiled: October 9, 2002Date of Patent: September 23, 2003Assignee: Analog Devices, Inc.Inventors: Frederic Boutaud, Sean M. FitzPatrick, Paul D. Krivacek
-
Patent number: 6624682Abstract: Described is an apparatus and a method for pulling an integrated circuit I/O pad to a known state and providing a current path between the pad and a source of potential during periods when an I/O voltage is likely to be floating. At least one I/O transistor coupled between the I/O pad and a source of potential is provided. Also provided is a combinatorial circuit connected to the I/O transistor to turn on the I/O transistor during periods that the I/O voltage is likely to be floating.Type: GrantFiled: October 9, 2002Date of Patent: September 23, 2003Assignee: Analog Devices, Inc.Inventors: Frederic Boutaud, Sean M. FitzPatrick, Paul D. Krivacek
-
Patent number: 6600345Abstract: A clock selection circuit for selecting one of a plurality of clocks as an output clock. When the selection circuit switches between two of the plurality of clocks for output, the currently output clock is removed from the output. The removal of the currently output clock is performed synchronously to the currently selected clock. The newly selected clock is then coupled to the output. Coupling of the newly selected clock is performed synchronously to the newly selected clock.Type: GrantFiled: November 15, 2001Date of Patent: July 29, 2003Assignee: Analog Devices, Inc.Inventor: Frederic Boutaud
-
Patent number: 6438720Abstract: A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.Type: GrantFiled: June 7, 1995Date of Patent: August 20, 2002Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Jason Jones, Marc Couvrat, Oliver Mougenot, Mansoor A. Chishtie
-
Patent number: 6334181Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: July 23, 1999Date of Patent: December 25, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
-
Patent number: 6311264Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: October 30, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
-
Patent number: 6263419Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: July 17, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
-
Patent number: 6263418Abstract: A data processing device is used with peripheral devices having addresses and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: July 17, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
-
Patent number: 6253307Abstract: A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.Type: GrantFiled: August 10, 1994Date of Patent: June 26, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
-
Patent number: 6249860Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: June 19, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
-
Patent number: 6249859Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: June 19, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
-
Patent number: 6247111Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: June 12, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig