Abstract: An electromechanical apparatus includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: A device including a screen memory (53) for storing the data relating to the points of a screen on which the curve is to be drawn. A point processor (21) modifies the data stored in the screen memory (53) at the positions of said screen memory corresponding to the points of the curve to be drawn. An address processor (20) adapted to control the access to the screen memory (53), the operation of the processor (21) and the transfers of data between the point processor (21) and the screen memory (53) so as to ensure the modification of its content as a function of the line to be drawn. A CROM memory (22) containing instructions relating to the changing of the reference of U, V relative coordinates of each octant change and instructions relating to the point by point drawings of portions of curves contained in each of the octants covered by the arc of a curve to be drawn.

Abstract: A data processing device is used with peripheral devices having addresses and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: This digital-analog conversion system comprises a digital modulator (1) having several quantification levels formed by a second order Delta-Sigma modulator and a digital-analog converter and switched capacitors filter set (3) whose law of progression between the different analog levels is independent of the absolute and relative values of the constituent components of the said assembly.

Abstract: A data processing device includes an instruction decoder and an arithmetic logic unit having first and second inputs and an output. An accumulator is connected between the output and first input of the arithmetic logic unit. A further register is connected between the accumulator and the second input of the arithmetic logic unit. The arithmetic logic unit includes circuitry for computing a digital value to the accumulator as well as an additional circuit. The additional circuit thereupon compares the value at the second input from said register with the digital value in the accumulator in response to a command from the instruction decoder and then stores to the register the lesser or the greater in value of the contents of the register and the digital value in the accumulator depending on the command. Other devices, systems and methods are also disclosed.

Abstract: This interpolative filter comprising N differentiating stages (4A-4N) constituting a section of low sampling frequency and N integrating stages (5A-5N) constituting a section of high sampling frequency is characterized in that is further comprises modulators (7A-7N) which are inserted into the string of integrators and which are intended to eliminate the increasing of the number of bits of the signal at each integration stage, and in that the said integrators are each included in a differentiation loop.

Abstract: This system includes a composite memory (5) in which are memorized the data for images to be displayed for each frame. A video display processor (12) controls the screen (8). A central processing unit (1) effects the composition of the image with the memory and an address processor (10), the extraction of the point data to be displayed being effected by a time base circuit (BT) synchronized with the sweeping of the screen, and by a control device (15) for dynamic access which distributes the access times among different units utilizing the memory. The memory (5) includes a first control memory for the memorization of a data word for a line or group of lines making up the image, each word having an address value for addressing a second control memory which contains, at each of these addresses, at least one display attribute data word characterizing the contents of the line(s) corresponding to the value of the respective address of the first control memory.

Abstract: The point processor includes a network of memory cells (33) addressable into rows and columns (direction X and Y). A control unit (42) effects reading and writing into the network according to parameters established in advance. This processor is integrated into a video display system for various image manipulations.