Abstract: A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.

Abstract: A method for implementing nonvolatile memory array logic includes configuring a crosspoint memory array in a first configuration and applying an input voltage to the crosspoint array in the first configuration to produce a setup voltage. The crosspoint array is configured in a second configuration and an input voltage is applied to the crosspoint array in the second configuration to produce a sense voltage. The setup voltage and the sense voltage compared to perform a logical operation on data stored in the crosspoint array. A system for performing nonvolatile memory array logic is also provided.

Abstract: In one example, a system includes a multi-plane memory array with shared crossbars and memory elements accessed through the shared crossbars and support circuitry. The support circuitry includes a bias multiplexer to determine an orientation of a target memory element in the multi-plane memory array and output voltage biases with a polarity based on the orientation of the target memory element. Methods for generating and applying geometry dependent voltage biases are also provided.

Abstract: In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.

Abstract: A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.

Abstract: Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell.

Abstract: A method includes applying a voltage bump across a combined memory device comprising a volatile selector switch and a nonvolatile switch, in which the voltage bump changes a state of the volatile selector switch from a high resistance to a low resistance but does not change a state of the nonvolatile switch. A read voltage that is lower than the voltage bump across the combined memory device to read a state of the nonvolatile switch.

Abstract: Dynamic/static random access memory (D/SRAM) cell, block shift static random access memory (BS-SRAM) and method using the same employ dynamic storage mode and dynamic storage mode switching to shift data. The D/SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, and a dynamic/static (D/S) mode selector to selectably switch the D/SRAM cell between the dynamic storage mode and a static storage mode. The BS-SRAM includes a plurality of D/SRAM cells arranged in an array and a controller to shift data from an adjacent D/SRAM cell in a second row of the array to a D/SRAM cell in a first row. The method includes switching the mode of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected D/SRAM cell.

Abstract: A method includes applying a voltage bump across a combined memory device comprising a volatile selector switch and a nonvolatile switch, in which the voltage bump changes a state of the volatile selector switch from a high resistance to a low resistance but does not change a state of the nonvolatile switch. A read voltage that is lower than the voltage bump across the combined memory device to read a state of the nonvolatile switch.

Abstract: In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar. array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.

Abstract: In one example, a system includes a multi-plane memory array with shared crossbars and memory elements accessed through the shared crossbars and support circuitry. The support circuitry includes a bias multiplexer to determine an orientation of a target memory element in the multi-plane memory array and output voltage biases with a polarity based on the orientation of the target memory element. Methods for generating and applying geometry dependent voltage biases are also provided.

Abstract: A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.

Abstract: A list sort static random access memory (LSSRAM) unit cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data and a dynamic/static (D/S) mode selector to selectably switch the LSSRAM unit cell between a dynamic storage mode and a static storage mode. The LSSRAM unit cell further includes a swap selector to swap the stored data with data stored in an adjacent memory cell during the dynamic storage mode when the swap selector is activated, and a data comparator to compare the stored data in the SRAM cell with the data stored in the adjacent memory cell and to activate the swap selector according to a result of the comparison.

Abstract: A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.

Abstract: Examples disclose a crossbar memory with a first crossbar to write data values corresponding to a word. The crossbar memory further comprises a second crossbar, substantially parallel to the first crossbar, to receive voltage for activation of data values across the second crossbar. Additionally, the examples of the crossbar memory provide an output line that interconnects with the crossbars at junctions, to read the data values at the junctions. Further, the examples of the crossbar memory provide a logic module to determine whether the second crossbar data values correspond to the word written in the first crossbar.

Abstract: A method for implementing nonvolatile memory array logic includes configuring a crosspoint memory array in a first configuration and applying an input voltage to the crosspoint array in the first configuration to produce a setup voltage. The crosspoint array is configured in a second configuration and an input voltage is applied to the crosspoint array in the second configuration to produce a sense voltage. The setup voltage and the sense voltage compared to perform a logical operation on data stored in the crosspoint array. A system for performing nonvolatile memory array logic is also provided.

Abstract: A dynamic sense circuit to determine memristor states within a memristor crossbar array that includes a differential comparator made up of a resistance capacitance (RC) network to capture a reference voltage and a differential pre-amp to operate in an open loop mode to dynamically compare the reference voltage to a sense voltage. An alternating current (AC) coupled amplifier receives the output of the comparator and outputs an amplified signal. A set-reset (SR) latch samples and holds the amplified signal as a digital value.

Abstract: A read circuit for sensing a resistance state of a resistive switching device in a crosspoint array utilizes a transimpedance equipotential preamplifier connected to a selected column line of the resistive switching device in the array. The equipotential preamplifier delivers a sense current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. A reference resistor is selectively connected to the equipotential preamplifier for setting a reference current, wherein the equipotential preamplifier is set to produce a preamplifier output voltage having a magnitude depending on whether the sense current is smaller or greater than the reference current. A voltage comparator is connected to the equipotential preamplifier to compare the preamplifier output voltage with a setup reference voltage and generate a comparator output voltage indicative of the resistance state of the resistive switching device.

Abstract: A list sort static random access memory (LSSRAM) unit cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data and a dynamic/static (D/S) mode selector to selectably switch the LSSRAM unit cell between a dynamic storage mode and a static storage mode. The LSSRAM unit cell further includes a swap selector to swap the stored data with data stored in an adjacent memory cell during the dynamic storage mode when the swap selector is activated, and a data comparator to compare the stored data in the SRAM cell with the data stored in the adjacent memory cell and to activate the swap selector according to a result of the comparison.

Abstract: A method for reading the state of a memory element within a crossbar memory array includes storing a first electric current sensed from a half-selected target memory element within the crossbar memory array; and outputting a final electric current based on the stored first electric current and a second electric current sensed from the target memory element when the target memory element is fully selected.