Abstract: A method of performing a read operation from a first magnetic random access memory (MRAM) cell in a memory cell string that includes the first MRAM cell coupled to a second MRAM cell. The method includes providing a voltage to a first end of the first memory cell string that is closest to the first MRAM cell, providing a ground source to a second end of the first memory cell string that is opposite the first end, and determining whether a voltage change occurred at a node between the first and second MRAM cells in response to applying a write sense current to the first MRAM cell.

Abstract: A combined analog and digital calibration circuit and method for adjusting an output offset voltage of a differential amplifier circuit are provided. The circuit comprises a digitally controlled voltage divider positioned between at least one isolated well and a controllable voltage source, a controllable voltage source controlled by an initial constant current and a variable current, and a controller to modify the variable current to continuously adjust the back gate control voltage. The method comprises adjusting a control voltage of at least one of a pair of input transistors using a back gate control voltage, providing an analog current to establish a back gate control voltage, and altering the analog current when the back gate control voltage causes an output offset voltage to differ from a reference voltage by more than a predetermined quantity.

Abstract: A method of making a lower cost active matrix display. In a particular embodiment, the method includes providing at least one first conductor upon a substrate and depositing a gate dielectric upon the first conductor and substrate. At least one paired second conductor and a pixel electrode are deposited upon the gate dielectric, with the second conductor crossing the first conductor and with a narrow gap between the paired second conductor and the pixel electrode. A semiconductor material is deposited over the paired second conductor and pixel electrode, filling the narrow gap. The narrow gap shelters a portion of the semiconductor material, which serves as a semiconductor bridge capable of functioning either as an insulator or as a channel region of a field effect transistor. The remaining, unsheltered semiconductor material is removed.

Abstract: In various embodiments of the present invention, tunable resistors are introduced at the interconnect layer of integrated circuits in order to provide a for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronic characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains.

Abstract: A magnetic memory cell write current threshold detector. The magnetic memory cell write current threshold detector includes a first MRAM test cell receiving a write current and sensing when the write current exceeds a first threshold, and a second MRAM test cell receiving the write current and sensing when the write current exceeds a second threshold.

Abstract: Programming of a programmable resistive memory device includes supplying programming power to the device; generating feedback as to when the device has been programmed; and removing the programming power when the feedback indicates that the device has been programmed.

Abstract: Methods and apparatuses are disclosed for controlling the write current in magnetic memory. In some embodiments, the method includes: providing a current in a plurality of memory write lines (where the write lines may be magnetically coupled to at least one memory element), coupling a first and second plurality of transistors to either end of the memory write line, and altering the conduction state of individual transistors within the first and second plurality of transistors.

Abstract: A digital current source used to mirror a reference current is provided. The digitally controlled analog current source multiplies a current from a master mirror transistor producing an output current that is a digitally controlled multiple of the reference current. The circuit comprises a plurality of one bit current mirror cells. Each one bit current mirror cell comprises a mirror transistor receiving an analog gate voltage from a master mirror transistor and providing a drain voltage, an operational amplifier configured to maintain the drain voltage for the mirror transistor equivalent to the analog gate voltage, and a switch configured to receive one control bit, the switch enabling current mirroring when the mirror voltage is substantially equivalent to the master mirror voltage. The digital current source further includes a common line summing element employed to receive and compile currents from each of the one bit current mirror cells.

Abstract: A combined analog and digital calibration circuit and method for adjusting an output offset voltage of a differential amplifier circuit are provided. The circuit comprises a digitally controlled voltage divider positioned between at least one isolated well and a controllable voltage source, a controllable voltage source controlled by an initial constant current and a variable current, and a controller to modify the variable current to continuously adjust the back gate control voltage. The method comprises adjusting a control voltage of at least one of a pair of input transistors using a back gate control voltage, providing an analog current to establish a back gate control voltage, and altering the analog current when the back gate control voltage causes an output offset voltage to differ from a reference voltage by more than a predetermined quantity.

Abstract: A memory device and method of reading the memory device is disclosed. The memory device includes a first string of MRAM cells and a second string of MRAM cells. The first string of MRAM cells include a plurality of MRAM cells connected in series and the second string of MRAM cells include another plurality of MRAM cells connected in series. A common connection is controllably connectable to one end of the first string of MRAM cells, and to one end of the second string of MRAM cells.

Abstract: A M by N bit synchronous counter for use in advanced applications is provided. The M by N bit synchronous counter comprises an M by N register configured to receive and store data corresponding to at least one word integrated with a N bit counter configured to sequentially count out a selected word of data from the M by N register. The present design replaces a single counter latch circuit with a plurality or stack of selectable latches and employs combined load/store logic and counter controls.

Abstract: An information storage device is provided. The information storage device may be a magnetic random access memory (MRAM) device including a resistive cross point array of spin dependent tunneling (SDT) junctions or magnetic memory elements, with word lines extending along rows of the SDT junctions and bit lines extending along the columns of the SDT junctions. The present design includes a plurality of heating elements connected in series with associated magnetic memory elements, each heating element comprising a diode. Voltage applied to a magnetic memory element and associated heating element causes reverse current to flow through the diode, thereby producing heat from the diode and heating the magnetic memory element, thereby facilitating the write function of the device.

Abstract: A M by N bit synchronous counter for use in advanced applications is provided. The M by N bit synchronous counter comprises an M by N register configured to receive and store data corresponding to at least one word integrated with a N bit counter configured to sequentially count out a selected word of data from the M by N register. The present design replaces a single counter latch circuit with a plurality or stack of selectable latches and employs combined load/store logic and counter controls.

Abstract: A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical defects. At manufacture, the MRAN device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data, using either a parametric evaluation (step 602), or a logical evaluation (step 603) or preferably a combination of both. Failed cells are identified and a count is formed, suitably in terms of ECC symbols 206 that would be affected by such failed cells (step 604). The count can be compared to a threshold (step 605) to determine suitability of the accessed storage cells and a decision made (step 606) on whether to continue with use of those cells, or whether to take remedial action.

Abstract: The invention includes an apparatus and method for selecting a desirable magnitude of a magnetic memory cell write current. The method includes determining a minimal magnitude of write current for writing to the magnetic memory cell, determining a maximal magnitude of write current for writing to the magnetic memory cell, and calculating the selected magnitude of magnetic memory cell write current based on the minimal magnitude of write current and the maximal magnitude of write current.

Abstract: Methods and apparatuses are disclosed for communicating data on a chip. In one embodiment, the method includes: reading the data value of a memory element utilizing conductors that are electrically coupled to the memory element, and communicating the value read from the memory element to other locations on chip using write conductors that are magnetically coupled to the memory element.

Abstract: A data storage device includes a cross point array of resistive memory elements and a plurality of blocking elements. The device is arranged in groups. Each group includes series-connected memory elements and a blocking element. The blocking elements are used to prevent sneak path currents from interfering with sense currents during read operations.

Abstract: A gain stage in a sense amplifier receives an input signal representing a stored value and senses if the input signal is less than or not less than a reference signal and generates an output signal indicative of a first state when the input signal is less than the reference signal and an output signal indicative of a second state when the input signal is not less than the reference signal. The gain stage further comprises an integrated latch configured to latch the output signal in either the first or second state. Additionally, a controller operates a sense amplifier having multiple operating modes. Sample mode switch logic causes the sense amplifier to sample a first voltage applied to the sense amplifier's input and hold and compare mode switch logic causes the sense amplifier to hold the first voltage for comparison with a second voltage applied to the sense amplifier's input.

Abstract: In various embodiments of the present invention, tunable resistors are introduced at the interconnect layer of integrated circuits in order to provide a means for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronic characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains.

Abstract: A storage device includes memory cells each including a magnetic element, where the memory cells include a first memory cell connected between a first voltage and a sense node, and at least second and third memory cells connected in parallel between the sense node and a reference voltage. A sampling circuit is coupled to the sense node, with the sampling circuit configured to receive a first voltage sample corresponding to an original state of the first memory cell, and to store a second voltage sample corresponding to a known state of the first memory cell after the first memory cell has been written to the known state. A differential amplifier compares the first and second voltage samples in their analog forms.