Abstract: A sense amplifier for reading the data stored in a crossbar array includes a storage transistor to store a first voltage resulting from an electric current from a column line connected to a target memory element while the target memory element is half-selected, the first voltage resulting from bias voltages applied to row lines not connected to the target memory element; a mirror transistor to store a second voltage resulting from an electric current from the column line while the target memory element is fully selected; a cross-coupled inverter circuit having a first branch connected to the storage transistor and a second branch connected to the mirror transistor; and an output node to output a signal from the first branch of the cross-coupled inverter circuit, the signal based on a comparison between the first voltage stored in the storage transistor and the second voltage across the mirror transistor.

Abstract: A method for reading the state of a memory element within a crossbar memory array includes storing a first electric current sensed from a half-selected target memory element within the crossbar memory array; and outputting a final electric current based on the stored first electric current and a second electric current sensed from the target memory element when the target memory element is fully selected.

Abstract: A method for reading a memory element within a crossbar array, the method including selecting a column line connected to a target memory element of the crossbar array by applying a supply voltage to a source follower, a gate terminal of the source follower connected to the column line; applying bias voltages to row lines of the crossbar array; storing an output voltage of the source follower in a storage element; applying a sense voltage to a row line connected to the target memory element; and outputting a difference between the voltage stored in the storage element and an output voltage of the source follower while the sense voltage is applied to the row line.

Abstract: A multi-plane circuit structure has at least a first circuit plane and a second circuit plane, and each circuit plane has a plurality of row wire segments, a plurality of column wire segments, and a plurality of crosspoint devices formed at intersections of the row wire segments and the column wire segments. The row and column wire segments have a segment length for forming a preselected number of crosspoint devices thereon. Each row wire segment in the second circuit plane is connected to a row wire segment in the first circuit plane with no offset in a row direction and in a column direction, and each column wire segment in the second circuit plane is connected to a column wire segment in the first circuit plane with an offset length in both the row direction and the column direction. The offset length corresponds to half of the preselected number of crosspoint devices.

Abstract: An extensible three dimensional circuit having parallel array channels includes an access layer and crossbar array layers overlying the access layer and being electrically connected to the access layer. The crossbar array layers include parallel channels, the parallel channels being formed from two classes of vias, the first class being pillar vias connected to relatively short stub lines, and the second class being traveling-line vias connected to long lines that travel away from the via; pillar vias and traveling-line vias being configured to connect to crossing lines such that each crossing point between the lines is uniquely addressed by one pillar via and one traveling-line via. Programmable crosspoint devices are disposed between the crossing lines.

Abstract: An interconnect architecture for connecting read/write circuitry to a memory structure, the interconnect architecture includes a switching layer having a number of access switches arranged in at least one set of two offset switch blocks, the access switches being connected to a first set of parallel wire tracks and a second set of parallel wire tracks intersecting the first set of parallel wire tracks; and a routing layer connecting the switches to a number of access vias of the memory structure; in which four wire tracks are used to select a programmable device of the memory structure.

Abstract: A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.

Abstract: A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.

Abstract: A sense amplifier for reading the data stored in a crossbar array includes a storage transistor to store a first voltage resulting from an electric current from a column line connected to a target memory element while the target memory element is half-selected, the first voltage resulting from bias voltages applied to row lines not connected to the target memory element; a mirror transistor to store a second voltage resulting from an electric current from the column line while the target memory element is fully selected; a cross-coupled inverter circuit having a first branch connected to the storage transistor and a second branch connected to the mirror transistor; and an output node to output a signal from the first branch of the cross-coupled inverter circuit, the signal based on a comparison between the first voltage stored in the storage transistor and the second voltage across the mirror transistor.

Abstract: A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage to a row line connected to the target memory element; and measuring an output current of the current mirror.

Abstract: A method for reading a memory element within a crossbar array, the method including selecting a column line connected to a target memory element of the crossbar array by applying a supply voltage to a source follower, a gate terminal of the source follower connected to the column line; applying bias voltages to row lines of the crossbar array; storing an output voltage of the source follower in a storage element; applying a sense voltage to a row line connected to the target memory element; and outputting a difference between the voltage stored in the storage element and an output voltage of the source follower while the sense voltage is applied to the row line.

Abstract: A method for reading the state of a memory element within a crossbar memory array includes storing a first electric current sensed from a half-selected target memory element within the crossbar memory array; and outputting a final electric current based on the stored first electric current and a second electric current sensed from the target memory element when the target memory element is fully selected.

Abstract: An extensible three dimensional circuit having parallel array channels includes an access layer and crossbar array layers overlying the access layer and being electrically connected to the access layer. The crossbar array layers include parallel channels, the parallel channels being formed from two classes of vias, the first class being pillar vias connected to relatively short stub lines, and the second class being traveling-line vias connected to long lines that travel away from the via; pillar vias and traveling-line vias being configured to connect to crossing lines such that each crossing point between the lines is uniquely addressed by one pillar via and one traveling-line via. Programmable crosspoint devices are disposed between the crossing lines.

Abstract: A data storage device includes non-volatile memory; and a read circuit for performing multi-sample read operations on the memory during a normal mode of operation. The read circuit includes a digital counter having an output that indicates a single bit (e.g., a sign-bit). The read circuit allows an external device (e.g., a memory tester) to supply test clock pulses to an input of the digital counter during a test mode. The test clock pulses can be counted to determine a state of the digital counter.

Abstract: A memory device and method of reading the memory device is disclosed. The memory device includes a first string of MRAM cells and a second string of MRAM cells. The first string of MRAM cells include a plurality of MRAM cells connected in series and the second string of MRAM cells include another plurality of MRAM cells connected in series. A common connection is controllably connectable to one end of the first string of MRAM cells, and to one end of the second string of MRAM cells.

Abstract: A digital current source used to mirror a reference current is provided. The digitally controlled analog current source multiplies a current from a master mirror transistor producing an output current that is a digitally controlled multiple of the reference current. The circuit comprises a plurality of one bit current mirror cells. Each one bit current mirror cell comprises a mirror transistor receiving an analog gate voltage from a master mirror transistor and providing a drain voltage, an operational amplifier configured to maintain the drain voltage for the mirror transistor equivalent to the analog gate voltage, and a switch configured to receive one control bit, the switch enabling current mirroring when the mirror voltage is substantially equivalent to the master mirror voltage. The digital current source further includes a common line summing element employed to receive and compile currents from each of the one bit current mirror cells.

Abstract: A method for making magnetic random access memories (MRAM) isolates each and every memory cell in an MRAM array during operation until selected. Some embodiments use series connected diodes for such electrical isolation. Only a selected one of the memory cells will then conduct current between respective ones of the bit and word lines. A better, more uniform distribution of read and data-write data access currents results to all the memory cells. In another embodiment, this improvement is used to increase the number of rows and columns to support a larger data array. In a further embodiment, such improvement is used to increase operating margins and reduce necessary data-write voltages and currents.

Abstract: A memory device includes a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, a second layer of MRAM memory cells that is fabricated over the first layer of MRAM memory cells, and a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device. The method of fabricating the memory device includes fabricating a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, fabricating a second layer of MRAM memory cells over the first layer of MRAM memory cells, and fabricating a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device.

Abstract: A memory storage device having an address control system is disclosed. The memory storage device includes memory cells and an address control system configured to decode a bit number which identifies a number of the memory cells which are selected in parallel. The memory cells selected in parallel correspond to least significant bits of an address which has a range that includes the memory cells.

Abstract: A flexible media magnetic printing system provides for data storage within flexible media imprinted with magnetic ink. In a particular embodiment, the printing system includes at least one reservoir of magnetic ink with magnetic particles capable of supporting high density data, and at least one reservoir of visible ink. The reservoirs are coupled to a print head including one or more ink-ejecting nozzles, which is removably or fixedly coupled to at least one magnetic read/write device. The magnetic read/write device tracks above the magnetic ink applied by the ink-ejecting nozzles to the flexible media. The magnetic read/write device writes to the magnetic ink by providing a magnetic field of sufficient intensity to re-orient the magnetic alignment within the ink to a known direction. The magnetic read/write device also reads data from flexible media, for example, paper or cloth that is imprinted with data-embedded magnetic ink.