Abstract: A magnetoresistive random access memory (MRAM) cell array device, which may be embodied in a resistive cross point memory (RXPtM) device, includes a chip (i.e., substrate) on which is formed an array of MRAM cells. Preferably, formed on this same chip is a controller effecting a setup algorithm for determining a most preferable write current (or currents) to be used in writing binary data bits into memory cells of the array while preserving data previously written into other memory cells of the array.

Abstract: A magnetic memory array is described having a plurality of bit cells. Each bit cell includes at least one magnetic layer having free magnetic poles with a corresponding demagnetization field. A magnetic flux absorbing layer is disposed between at least two of the plurality of bit cells.

Abstract: Methods and apparatuses are disclosed for controlling the write current in magnetic memory. In some embodiments, the method includes: providing a current in a plurality of memory write lines (where the write lines may be magnetically coupled to at least one memory element), coupling a first and second plurality of transistors to either end of the memory write line, and altering the conduction state of individual transistors within the first and second plurality of transistors.

Abstract: Methods and apparatuses are disclosed for reducing the read time of a memory array. In one embodiment, the method includes: sampling unknown data values from a plurality of memory elements, buffering the unknown values, writing known values to the plurality of memory elements and sampling the known values, and comparing the known values to the buffered values.

Abstract: Method and apparatus for coupling conductors in magnetic memory. In some embodiments, the memory element comprises: a first magnetic memory element, a first group of conductors magnetically coupled to the first magnetic memory element, a second magnetic memory element, a second group of conductors magnetically coupled to the second magnetic memory element, where the second magnetic memory element is substantially vertical to the first, and the first and second group of conductors have at least one conductor in common.

Abstract: Disclosed herein are systems and devices having memories with reference-initiated sequential sensing. In one embodiment, a reference-initiated sequential sensing method comprises: forming a first attribute measurement associated with a stored data value in a first memory element; using the first memory element to determine a decision threshold; comparing the first attribute measurement to the decision threshold to determine the stored data value in the first memory element; forming a subsequent attribute measurement associated with a stored data value in a subsequent memory element; and comparing the subsequent attribute value to the decision threshold to determine a data value stored in the subsequent memory element.

Abstract: A storage device includes memory cells each including a magnetic element, where the memory cells include a first memory cell connected between a first voltage and a sense node, and at least second and third memory cells connected in parallel between the sense node and a reference voltage. A sampling circuit is coupled to the sense node, with the sampling circuit configured to receive a first voltage sample corresponding to an original state of the first memory cell, and to store a second voltage sample corresponding to a known state of the first memory cell after the first memory cell has been written to the known state. A differential amplifier compares the first and second voltage samples in their analog forms.

Abstract: The invention includes an apparatus and method for regulating a magnetic memory cell write current. The method includes modifying a magnetic memory cell write current by summing a write current offset to the magnetic memory cell write current, and determining whether writing to a magnetic memory cell with the modified magnetic memory cell write current results in a write error condition. If a write error condition exists, then the method includes incrementing the magnetic memory cell write current, or decrementing the magnetic memory cell write current, until the write error condition is eliminated.

Abstract: The invention includes a parallel processor. The parallel processor includes a plurality of non-volatile memory cells. The parallel processor additionally includes a plurality of processor elements. At least one non-volatile memory cell corresponds with each of the processor elements. The processor elements each access data from at least one corresponding non-volatile memory cell. The processor elements perform processing on the data. The non-volatile memory cells can include magnetic memory cells.

Abstract: A magnetic memory which detects changes between resistive states of a memory cell is disclosed. In one embodiment the magnetic memory includes a memory cell which has first and second resistive states. First and second write conductors are configured to conduct first and second currents to change the memory cell between the first and the second resistive states. The first and the second write conductors are routed in first and second directions and intersect the memory cell. First and second sense conductors are configured to conduct a sense current through the memory cell. A sense circuit coupled to the second sense conductor is configured to detect the change between the first and the second resistive states.

Abstract: A memory apparatus, which may be of resistive cross point memory (RXPtM) cell type (one example of which is a magnetic random access memory (MRAM)) includes multiple serial data paths which are merged and may exchange data as needed by the data input/output (I/O) circuits connected to a serial I/O port. A plurality of scan path registers are connected by an array of static random access memory (SRAM) memory units of plural memory cells. The scan paths and SRAM memory units perform a parallel transfer of data from scan path registers to and from temporary registers of the SRAM memory units in order to effect parallel data exchange between the multiple scan path registers.

Abstract: Methods, systems, and programs for recalibrating a sense amplifier are disclosed.

Abstract: A method for performing a read operation from a memory cell in a memory cell string is provided. The method includes applying a constant current across the memory cell string, measuring a first voltage across the memory cell string, writing the memory cell to a first state, measuring a second voltage across the memory cell string, and determining whether the first voltage differs from the second voltage.

Abstract: A method for performing a read operation from a magnetic random access memory (MRAM) cell in a memory cell string is provided. The method includes applying a constant current through the memory cell string, measuring a first voltage across the memory cell string, applying a write sense current across the MRAM cell, measuring a second voltage across the memory cell string, and determining whether the first voltage differs from the second voltage.

Abstract: A method of performing a read operation from a first memory cell in a memory cell string that includes a first memory cell coupled to a second memory cell. The method includes providing a voltage to a first end of the first memory cell string that is closest to the first memory cell, providing a ground source to a second end of the first memory cell string that is opposite the first end, and determining whether a voltage change occurred at a node between the first and second memory cells in response to writing the first memory cell to a first state.

Abstract: A data storage device that includes a memory cell string. The memory cell string includes a first memory cell and a second memory cell. The device also includes a circuit coupled to a node between the first memory cell and a second memory cell. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and the first memory cell being written to a first state.

Abstract: A method of performing a read operation from a first magnetic random access memory (MRAM) cell in a memory cell string that includes the first MRAM cell coupled to a second MRAM cell. The method includes providing a voltage to a first end of the first memory cell string that is closest to the first MRAM cell, providing a ground source to a second end of the first memory cell string that is opposite the first end, and determining whether a voltage change occurred at a node between the first and second MRAM cells in response to applying a write sense current to the first MRAM cell.

Abstract: A data storage device comprising a first memory cell string that includes at least a first magnetic random access memory (MRAM) cell coupled to a second MRAM cell and a circuit coupled to a node between the first MRAM cell and the second MRAM cell is provided. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and in response to a write sense current being applied across the first MRAM cell.

Abstract: A four-conductor MRAM device comprising an array of memory cells, each of the memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to the first magnetic layer of the array of memory cells; a plurality of local row sense lines wherein one of the local row sense lines is electrically connected to the second magnetic layer of the array of memory cells; a plurality of global column write lines parallel to the plurality of local column sense lines; a plurality of global row write lines parallel to the plurality of local row sense lines; and wherein the plurality of local column sense lines and the plurality of local row sense lines are connected to read data from the array of memory cells and the plurality of global column write lines and the plurality of global row write lines are connected to write data to the array of memory cells.

Abstract: Systems and methods for reading from or writing to memory blocks, are provided. An embodiment of the system comprises a plurality of memory blocks; a plurality of repeaters; and a line that couples the memory blocks with the repeaters such that the repeaters can read from the memory blocks. One embodiment of the method comprises coupling the memory blocks to repeaters; and reading from the memory blocks.