Abstract: A three-dimensional (3D) flash memory device is provided. The 3D flash memory device includes a substrate, a T-shaped polysilicon pillar, a select line pillar, a bit line pillar, first and second control gates, first and second floating gates, and first and second high-k dielectric pillars. The select line pillar and the bit line pillar are vertically disposed adjacent to first opposite sidewalls of the horizontally protruding portion on the substrate. The first control gate and the second control gate are positioned adjacent to second opposite sidewalls of the horizontally protruding portion. The first and second floating gates are laterally disposed between the horizontally protruding portion and the first and second control gates. The first and second high-k dielectric pillars are laterally disposed between the first floating gate and the first control gate, as well as between the second floating gate and the second control gate.

Abstract: Provided is a flash memory device including a gate stack structure, at least three channel pillars, a charge storage structure, at least three source line, and at least three bit lines. The gate stack structure is disposed above a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately each other. The at least three channel pillars extend through the gate stack structure. The at least three channel pillars are electrically isolated from one another. The charge storage structure is disposed between the plurality of gate layers and the at least three channel pillars. The at least three source line are disposed below the gate stack structure and electrically connected to the at least three channel pillars. The at least three bit lines are disposed above the gate stack structure, and electrically connected to the at least three channel pillars.

Abstract: A flash memory cell includes a channel structure, a first gate, a second gate, a storage structure, a source line pillar and a bit line pillar. The channel structure is formed over a substrate. The first gate is formed adjacent to the channel structure. The second gate is separated from the first gate and the channel structure. The storage structure is adjacent to the channel structure. The source line pillar and the bit line pillar are respectively adjacent to opposite sidewalls of the channel structure. The first gate does not vertically overlap with the channel structure.

Abstract: A DRAM is provided. In the DRAM, on a substrate, first and second channel layers are separated in a first direction. A storage node is disposed between the first and second channel layers. A bit line is disposed at one side of the first channel layer away from the storage node. A word line and a first conductive are respectively disposed at opposite sides of the first channel layer in a second direction. A first dielectric layer is disposed between the word line and the first channel layer. A second dielectric layer is disposed between the storage node and the second channel layer. A second conductive is disposed at one side of the second channel layer away from the storage node. A source line and a drain line are respectively disposed at opposite sides of the second channel layer in the second direction.

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.

Abstract: A semiconductor memory device includes a plurality of nanowires vertically stacked over a substrate, and a plurality of memory films wrapping around the plurality of nanowires, respectively. Each of the memory films includes a first oxide layer, a nitride layer and a second oxide layer sequentially formed over the corresponding nanowire. The semiconductor memory device also includes a gate electrode layer surrounding the plurality of memory films, and an isolation structure encapsulating the gate electrode layer. The isolation structure is in direct contact with the gate electrode layer and the nitride layers of the memory films.

Abstract: A semiconductor device, including a semiconductor substrate; an isolation feature on the semiconductor substrate; a plurality of strip-shaped active regions defined by the isolation feature, wherein a column position of an edge of each of the strip-shaped active regions in one row is laterally shifted by a shift distance relative to a column position of a respective edge of each of the strip-shaped active regions in an adjacent row, and the shift distance is one to two times a width of the strip-shaped active regions; and capacitor contacts on both ends of each of the strip-shaped active regions.

Abstract: A three-dimensional (3D) flash memory device is provided. The 3D flash memory device includes a substrate, a T-shaped polysilicon pillar, a select line pillar, a bit line pillar, first and second control gates, first and second floating gates, and first and second high-k dielectric pillars. The select line pillar and the bit line pillar are vertically disposed adjacent to first opposite sidewalls of the horizontally protruding portion on the substrate. The first control gate and the second control gate are positioned adjacent to second opposite sidewalls of the horizontally protruding portion. The first and second floating gates are laterally disposed between the horizontally protruding portion and the first and second control gates. The first and second high-k dielectric pillars are laterally disposed between the first floating gate and the first control gate, as well as between the second floating gate and the second control gate.

Abstract: A method of forming semiconductor device, including forming a first protective strip and a second protective strip on a semiconductor substrate. The first protective strip and the second protective strip extend in a first direction and are alternately arranged in a second direction perpendicular to the first direction. The first protective strip and the second protective strip are spaced apart from each other. The first protective strip is cut by selectively removing a portion of the first protective strip. The second protective strip is cut by selectively removing a portion of the second protective strip. The semiconductor substrate is etched to form an isolation trench. Remaining portions of the first and second protective strips are removed. An isolation feature is filled into the isolation trench. The isolation feature defines a plurality of strip-shaped active regions. Capacitor contacts are formed on both ends of each of the strip-shaped active regions.

Abstract: Provided is a flash memory device including a gate stack structure, at least three channel pillars, a charge storage structure, at least three source line, and at least three bit lines. The gate stack structure is disposed above a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately each other. The at least three channel pillars extend through the gate stack structure. The at least three channel pillars are electrically isolated from one another. The charge storage structure is disposed between the plurality of gate layers and the at least three channel pillars. The at least three source line are disposed below the gate stack structure and electrically connected to the at least three channel pillars. The at least three bit lines are disposed above the gate stack structure, and electrically connected to the at least three channel pillars.

Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.

Abstract: A semiconductor memory device includes a substrate, and a plurality of layers vertically stacked over the substrate. A first layer in the plurality of layers includes an active region extending in a first direction parallel to a top surface of the substrate. The semiconductor memory device also includes a first conductive line that extends vertically in a second direction perpendicular to the top surface of the substrate and penetrates through the active region. The semiconductor memory device also includes a capacitor including a first electrode that is disposed in the active region.

Abstract: A resistive memory apparatus including bit lines, word lines, a memory array, bypass paths, select circuits, and a switch circuit is provided. The word lines are respectively crossed with the bit lines. The memory array includes memory elements. One end of each of the memory elements is coupled to the corresponding word line, and another end of each of the memory elements is coupled between a first node and a second node on the corresponding bit line. Each of the bypass paths is connected in parallel with the corresponding bit line between the first node point and the second node. Each of the select circuits is coupled to the corresponding bit line and bypass path, and configured to select the coupled bit line or bypass path. The switch circuit is coupled to the word lines, and configured to select one of the word lines.

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.

Abstract: Provided is a memory device including a stack structure, a plurality of channel layers, a source line, a bit line, a switching layer, and a dielectric pillar. The stack structure has a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel layers are respectively embedded in the conductive layers. The source line penetrates through the stack structure to be electrically connected to the channel layers at first sides of the channel layers. The bit line penetrates through the stack structure to be coupled to the channel layers at second sides of the channel layers. The switching layer wraps the bit line to contact the channel layers at the second sides of the channel layers. The dielectric pillar penetrates through the channel layers to divide each channel layer into a doughnut shape. A method of manufacturing a memory device is also provided.

Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether increasing rate of saturating read current is less than first threshold value; when increasing rate of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether increasing rate of saturating read current is less than first threshold value; finishing the method when increasing rate of saturating read current is less than first threshold value and saturating read current reaches target current value.

Abstract: A resistive memory apparatus including bit lines, word lines, a memory array, bypass paths, select circuits, and a switch circuit is provided. The word lines are respectively crossed with the bit lines. The memory array includes memory elements. One end of each of the memory elements is coupled to the corresponding word line, and another end of each of the memory elements is coupled between a first node and a second node on the corresponding bit line. Each of the bypass paths is connected in parallel with the corresponding bit line between the first node point and the second node. Each of the select circuits is coupled to the corresponding bit line and bypass path, and configured to select the coupled bit line or bypass path. The switch circuit is coupled to the word lines, and configured to select one of the word lines.

Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.

Abstract: A method of forming semiconductor device, including forming a first protective strip and a second protective strip on a semiconductor substrate. The first protective strip and the second protective strip extend in a first direction and are alternately arranged in a second direction perpendicular to the first direction. The first protective strip and the second protective strip are spaced apart from each other. The first protective strip is cut by selectively removing a portion of the first protective strip. The second protective strip is cut by selectively removing a portion of the second protective strip. The semiconductor substrate is etched to form an isolation trench. Remaining portions of the first and second protective strips are removed. An isolation feature is filled into the isolation trench. The isolation feature defines a plurality of strip-shaped active regions. Capacitor contacts are formed on both ends of each of the strip-shaped active regions.