Patents by Inventor Frederick Chen
Frederick Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11055021Abstract: A resistive memory including a storage array, a storage circuit, a control circuit, a voltage generation circuit and an access circuit is provided. The storage array includes a plurality of blocks. Each block includes a plurality of memory cells. The storage circuit stores a plurality of count values. Each of the count values indicates the number of times that a corresponding block performs a write operation. The control circuit generates a control signal according to the count values when an external command is a write command. The voltage generation circuit provides an operation voltage group according to the control signal. The access circuit accesses the storage array according to the operation voltage group.Type: GrantFiled: March 14, 2019Date of Patent: July 6, 2021Assignee: WINBOND ELECTRONICS CORP.Inventors: Ping-Kun Wang, Shao-Ching Liao, Chien-Min Wu, Chia Hua Ho, Frederick Chen, He-Hsuan Chao, Seow-Fong Lim
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Patent number: 11024511Abstract: Provided is a patterning method including: providing a strip layer with a plurality of strips A, in combination with a plurality of strips B and strips C arranged alternately between the strips A; forming a first mask layer having a first opening on the strip layer; removing the strips A and B exposed by the first opening; forming a plurality of first spacers on sidewalls defined by the first opening; forming a plurality of second spacers on sidewalls of the first spacers respectively; forming a second mask layer having a second opening on the strip layer; removing the strips A and C exposed by the second opening; forming a plurality of third spacers defined by the second opening; forming a plurality of fourth spacers on sidewalls of the third spacers respectively; and removing the strips A, the first spacers, and the third spacers to form a pattern layer.Type: GrantFiled: April 21, 2020Date of Patent: June 1, 2021Assignee: Winbond Electronics Corp.Inventor: Frederick Chen
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Patent number: 11024802Abstract: Provided is a method of fabricating a resistive memory including forming a first electrode and a second electrode opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer between the variable resistance layer and the second electrode; and forming a protection layer at least covering sidewalls of the oxygen exchange layer.Type: GrantFiled: November 14, 2019Date of Patent: June 1, 2021Assignee: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
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Publication number: 20210151504Abstract: A resistive random access memory (RRAM) device is provided. The RRAM device includes a gate structure on a substrate, and a source region and a drain region disposed on opposite sides of the gate structure on the substrate. The source region includes a semiconductor bulk, and the drain region includes a plurality of semiconductor fins adjacent to the semiconductor bulk, wherein the semiconductor fins are separated from each other by an isolation layer. The RRAM device further includes a plurality of RRAM units, wherein each of the RRAM units electrically contacts one of the semiconductor fins.Type: ApplicationFiled: November 14, 2019Publication date: May 20, 2021Inventor: Frederick CHEN
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Patent number: 11011231Abstract: A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.Type: GrantFiled: April 15, 2020Date of Patent: May 18, 2021Assignee: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Chang-Tsung Pai, Yu-Ting Chen, He-Hsuan Chao, Ming-Che Lin, Frederick Chen
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Publication number: 20210074356Abstract: A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.Type: ApplicationFiled: April 15, 2020Publication date: March 11, 2021Applicant: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Chang-Tsung Pai, Yu-Ting Chen, He-Hsuan Chao, Ming-Che Lin, Frederick Chen
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Patent number: 10847578Abstract: A three-dimensional resistive memory is provided. The three-dimensional resistive memory includes a resistive switching pillar, an electrode pillar disposed within the resistive switching pillar, a stack of bit lines adjacent to the resistive switching pillar, a plurality of sidewall contacts between each of the bit lines and the resistive switching pillar, and a selector pillar extending through the stack of bit lines. The bit lines are separated vertically from each other by an insulating layer. The selector pillar contacts each of the sidewall contacts.Type: GrantFiled: July 3, 2019Date of Patent: November 24, 2020Assignee: Windbond Electronics Corp.Inventor: Frederick Chen
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Patent number: 10756264Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.Type: GrantFiled: September 12, 2018Date of Patent: August 25, 2020Assignee: Winbond Electronics Corp.Inventor: Frederick Chen
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Patent number: 10636484Abstract: A memory device including a plurality of memory units; at least one geometric mean operator coupled to at least two of the plurality of memory units; and a memory state reader coupled to the at least one geometric mean operator to read a memory state of the plurality of memory units.Type: GrantFiled: September 12, 2018Date of Patent: April 28, 2020Assignee: Winbond Electronics CorporationInventors: Frederick Chen, Ping-Kun Wang, Chih-Cheng Fu, Chien-Min Wu
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Patent number: 10593877Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.Type: GrantFiled: April 10, 2018Date of Patent: March 17, 2020Assignee: Winbond Electronics Corp.Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Po-Yen Hsu, Yi-Hsiu Chen, Ting-Ying Shen, Bo-Lun Wu, Meng-Hung Lin, Chia-Hua Ho, Ming-Che Lin
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Publication number: 20200083446Abstract: Provided is a method of fabricating a resistive memory including forming a first electrode and a second electrode opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer between the variable resistance layer and the second electrode; and forming a protection layer at least covering sidewalls of the oxygen exchange layer.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Applicant: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
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Publication number: 20200082879Abstract: A memory device including a plurality of memory units; at least one geometric mean operator coupled to at least two of the plurality of memory units; and a memory state reader coupled to the at least one geometric mean operator to read a memory state of the plurality of memory units.Type: ApplicationFiled: September 12, 2018Publication date: March 12, 2020Inventors: Frederick CHEN, Ping-Kun WANG, Chih-Cheng FU, Chien-Min WU
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Patent number: 10522755Abstract: Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.Type: GrantFiled: March 9, 2016Date of Patent: December 31, 2019Assignee: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
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Publication number: 20190369920Abstract: A resistive memory including a storage array, a storage circuit, a control circuit, a voltage generation circuit and an access circuit is provided. The storage array includes a plurality of blocks. Each block includes a plurality of memory cells. The storage circuit stores a plurality of count values. Each of the count values indicates the number of times that a corresponding block performs a write operation. The control circuit generates a control signal according to the count values when an external command is a write command. The voltage generation circuit provides an operation voltage group according to the control signal. The access circuit accesses the storage array according to the operation voltage group.Type: ApplicationFiled: March 14, 2019Publication date: December 5, 2019Inventors: Ping-Kun WANG, Shao-Ching LIAO, Chien-Min WU, Chia Hua HO, Frederick CHEN, He-Hsuan CHAO, Seow-Fong LIM
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Patent number: 10497865Abstract: An RRAM device is provided, which includes a bottom electrode in an oxide layer, a plurality of dielectric protrusions on the oxide layer, wherein the bottom electrode is disposed between the two adjacent dielectric protrusions. A resistive switching layer is conformally disposed on the dielectric protrusions, the oxide layer, and the bottom electrode. A conductive oxygen reservoir layer is disposed on the resistive switching layer, and an oxygen diffusion barrier layer is disposed on the conductive oxygen reservoir layer.Type: GrantFiled: January 8, 2019Date of Patent: December 3, 2019Assignee: WINBOND ELECTRONICS CORP.Inventor: Frederick Chen
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Patent number: 10490739Abstract: A method of forming a one-time-programmable resistive random access memory bit includes forming a resistive switching layer on a bottom electrode layer. The method also includes forming a top electrode layer on the resistive switching layer. The method also includes applying a forming voltage to the resistive switching layer, such that the electric potential of the top electrode layer is lower than that of the bottom electrode layer. The method also includes performing a bake process on the resistive switching layer. The vacancies in the resistive switching layer are randomly distributed.Type: GrantFiled: January 10, 2018Date of Patent: November 26, 2019Assignee: Winbond Electronics Corp.Inventors: Frederick Chen, Ping-Kun Wang, Chih-Cheng Fu, Chien-Min Wu, Shao-Ching Liao
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Patent number: 10468458Abstract: A resistive random access memory includes a memory cell disposed at an intersection point between a first conductive line and a second conductive line. The memory cell includes a selector structure, a first current limiter structure and a resistor structure. The first current limiter structure is disposed between the selector structure and the first conductive line. The resistor structure is disposed between the selector structure and the second conductive line or between the first current limiter structure and the first conductive line.Type: GrantFiled: May 10, 2016Date of Patent: November 5, 2019Assignee: Winbond Electronics Corp.Inventor: Frederick Chen
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Publication number: 20190213468Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Frederick CHEN, Ping-Kun WANG, Shao-Ching LIAO, Chih-Cheng FU, Ming-Che LIN, Yu-Ting CHEN, Seow-Fong (Dennis) LIM
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Publication number: 20190214556Abstract: A method of forming a one-time-programmable resistive random access memory bit includes forming a resistive switching layer on a bottom electrode layer. The method also includes forming a top electrode layer on the resistive switching layer. The method also includes applying a forming voltage to the resistive switching layer, such that the electric potential of the top electrode layer is lower than that of the bottom electrode layer. The method also includes performing a bake process on the resistive switching layer. The vacancies in the resistive switching layer are randomly distributed.Type: ApplicationFiled: January 10, 2018Publication date: July 11, 2019Inventors: Frederick CHEN, Ping-Kun WANG, Chih-Cheng FU, Chien-Min WU, Shao-Ching LIAO
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Publication number: 20190140170Abstract: An RRAM device is provided, which includes a bottom electrode in an oxide layer, a plurality of dielectric protrusions on the oxide layer, wherein the bottom electrode is disposed between the two adjacent dielectric protrusions. A resistive switching layer is conformally disposed on the dielectric protrusions, the oxide layer, and the bottom electrode. A conductive oxygen reservoir layer is disposed on the resistive switching layer, and an oxygen diffusion barrier layer is disposed on the conductive oxygen reservoir layer.Type: ApplicationFiled: January 8, 2019Publication date: May 9, 2019Inventor: Frederick CHEN