Abstract: An RRAM device is provided, which includes a bottom electrode in an oxide layer, a plurality of dielectric protrusions on the oxide layer, wherein the bottom electrode is disposed between the two adjacent dielectric protrusions. A resistive switching layer is conformally disposed on the dielectric protrusions, the oxide layer, and the bottom electrode. A conductive oxygen reservoir layer is disposed on the resistive switching layer, and an oxygen diffusion barrier layer is disposed on the conductive oxygen reservoir layer.

Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.

Abstract: A resistive random access memory is provided. The resistive memory cell includes a substrate, a transistor on the substrate, a bottom electrode on the substrate and electrically connected to the transistor source/drain, several top electrodes on the bottom electrode, several resistance-switching layers between the top and bottom electrode, and several current limiting layers between the resistance-switching layer and top electrodes. The cell could improve the difficulty on recognizing 1/0 signal by current at high temperature environment and save the area on the substrate by generating several conductive filaments at one transistor location.

Abstract: Provided are a semiconductor device including a plurality of transistors and a plurality of memory cells. Each of the transistors includes a gate structure and a source/drain region. The memory cells are respectively located over the gate structures. A lower electrode of each of the memory cells and an upper electrode of an adjacent memory cell are electrically connected to the source/drain region between corresponding two transistors.

Abstract: Provided are a semiconductor device including a plurality of transistors and a plurality of memory cells. Each of the transistors includes a gate structure and a source/drain region. The memory cells are respectively located over the gate structures. A lower electrode of each of the memory cells and an upper electrode of an adjacent memory cell are electrically connected to the source/drain region between corresponding two transistors.

Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.

Abstract: A data read method and a non-volatile memory apparatus using the same are provided. The data read method includes: obtaining a first read current and a second read current from a memory cell pair of the non-volatile memory; performing a calculation operation according to the first read current and the second read current to obtain a calculation result; and determining a logical state of the memory cell pair according to the calculation result. The calculation operation includes at least a signal addition operation and a signal multiplying operation.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.

Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.

Abstract: Provided is a three-dimensional resistive memory including a channel pillar, a first gate pillar, a first gate dielectric layer, first and second stacked structures, a variable resistance pillar and an electrode pillar. The channel pillar is on a substrate. The first gate pillar is on the substrate and at a first side of the channel pillar. The first gate dielectric layer is between the channel pillar and the first gate pillar. The first and second stacked structures are on the substrate and respectively at opposite second and third sides of the channel pillar. Each of the first and second stacked structures includes conductive material layers and insulating material layers alternately stacked. The variable resistance pillar is on the substrate and at a side of the first stacked structure opposite to the channel pillar. The electrode pillar is on the substrate and inside of the variable resistance pillar.

Abstract: An operating method for a resistive memory cell and a resistive memory are provided. The operating method for the resistive memory cell includes following steps. A forming operation for the resistive memory cell is performed. Whether the resistive memory cell is in a first state is determined, wherein the first state is corresponding to a first operation. When the resistive memory cell is not in the first state, a complementary switching operation regarding a second operation for the resistive memory cell is performed, so that the resistive memory cell generates a complementary switching phenomenon regarding the second operation. Thus, the resistive memory cell which cannot retain data by normal forming operation can effectively obtain the data retention capability by the complementary switching phenomenon.

Abstract: A resistive random access memory includes a memory cell disposed at an intersection point between a first conductive line and a second conductive line. The memory cell includes a selector structure, a first current limiter structure and a resistor structure. The first current limiter structure is disposed between the selector structure and the first conductive line. The resistor structure is disposed between the selector structure and the second conductive line or between the first current limiter structure and the first conductive line.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance changeable layer, an oxygen reservoir layer and a reactive oxygen barrier layer. The bottom electrode is disposed on a substrate. The top electrode is disposed above the bottom electrode. The resistance changeable layer is disposed between the bottom electrode and the top electrode. The oxygen reservoir layer is disposed between the resistance changeable layer and the top electrode. The reactive oxygen barrier layer is disposed inside the oxygen reservoir layer.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance changeable layer, an oxygen reservoir layer and a reactive oxygen barrier layer. The bottom electrode is disposed on a substrate. The top electrode is disposed above the bottom electrode. The resistance changeable layer is disposed between the bottom electrode and the top electrode. The oxygen reservoir layer is disposed between the resistance changeable layer and the top electrode. The reactive oxygen barrier layer is disposed inside the oxygen reservoir layer.

Abstract: Provided is a three-dimensional resistive memory including a channel pillar, a first gate pillar, a first gate dielectric layer, first and second stacked structures, a variable resistance pillar and an electrode pillar. The channel pillar is on a substrate. The first gate pillar is on the substrate and at a first side of the channel pillar. The first gate dielectric layer is between the channel pillar and the first gate pillar. The first and second stacked structures are on the substrate and respectively at opposite second and third sides of the channel pillar. Each of the first and second stacked structures includes conductive material layers and insulating material layers alternately stacked. The variable resistance pillar is on the substrate and at a side of the first stacked structure opposite to the channel pillar. The electrode pillar is on the substrate and inside of the variable resistance pillar.

Abstract: A writing method for a resistive memory cell and a resistive memory using thereof are provided. In the writing method, a group of RESET signals is provided to the resistive memory cell, so as to execute a writing operation. A current of the resistive memory cell is detected to determine whether the writing operation of the resistive memory cell is completed. When the writing operation of the resistive memory cell is not completed, widths of filament paths in the resistive memory cell are determined to be narrowed or not. The voltage of word line of the resistive memory cell in the group of RESET signals is reduced when the widths of the filament paths in the resistive memory cell are narrowed.

Abstract: A resistive random access memory device includes a bottom electrode, a plurality of memory stacks separately formed over the bottom electrode, a third oxygen diffusion barrier layer formed between the memory stacks, and a top electrode formed over the plurality of memory stacks and the third oxygen diffusion barrier layer. Each of the plurality of memory stacks includes a resistive switching layer formed over the bottom electrode, a first oxygen diffusion barrier layer formed over the resistive switching layer, a conductive oxygen reservoir layer formed over the first oxygen diffusion barrier layer, and a second oxygen diffusion barrier layer formed over the conductive oxygen reservoir layer.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.

Abstract: Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.