Abstract: An RRAM device is provided, which includes a bottom electrode in an oxide layer, a plurality of dielectric protrusions on the oxide layer, wherein the bottom electrode is disposed between the two adjacent dielectric protrusions. A resistive switching layer is conformally disposed on the dielectric protrusions, the oxide layer, and the bottom electrode. A conductive oxygen reservoir layer is disposed on the resistive switching layer, and an oxygen diffusion barrier layer is disposed on the conductive oxygen reservoir layer.

Abstract: A resistive random access memory device is provided, which includes a bottom electrode, a resistive switching layer disposed on the bottom electrode, an oxidizable layer disposed on the resistive switching layer, a first oxygen diffusion barrier layer disposed between the oxidizable layer and the resistive switching layer, and a second oxygen diffusion barrier layer disposed on the oxidizable layer.

Abstract: An operating method for a resistive memory cell and a resistive memory are provided. The operating method for the resistive memory cell includes following steps. A forming operation for the resistive memory cell is performed. Whether the resistive memory cell is in a first state is determined, wherein the first state is corresponding to a first operation. When the resistive memory cell is not in the first state, a complementary switching operation regarding a second operation for the resistive memory cell is performed, so that the resistive memory cell generates a complementary switching phenomenon regarding the second operation. Thus, the resistive memory cell which cannot retain data by normal forming operation can effectively obtain the data retention capability by the complementary switching phenomenon.

Abstract: A writing method for a resistive memory apparatus is provided. In the method, logic data is received, and a corresponding selection memory cell is selected. A logic level of the logic data is determined. When the logic data is at a first logic level, a RESET pulse is provided to the selection memory cell and then a SET pulse smaller than a reference write current and having a near-rectangular pulse width is provided to the selection memory cell during a writing period. When the logic data is at a second logic level, the RESET pulse is provided to the selection memory cell and then a SET pulse larger than the reference write current and having the near-rectangular pulse width is provided to the selection memory cell during the writing period.

Abstract: A resistive random access memory is provided. The resistive memory cell includes a substrate, a transistor on the substrate, a bottom electrode on the substrate and electrically connected to the transistor source/drain, several top electrodes on the bottom electrode, several resistance-switching layers between the top and bottom electrode, and several current limiting layers between the resistance-switching layer and top electrodes. The cell could improve the difficulty on recognizing 1/0 signal by current at high temperature environment and save the area on the substrate by generating several conductive filaments at one transistor location.

Abstract: A writing method for a resistive memory apparatus is provided. In the method, logic data is received, and a corresponding selection memory cell is selected. A logic level of the logic data is determined. When the logic data is at a first logic level, a RESET pulse is provided to the selection memory cell and then a SET pulse smaller than a reference write current and having a near-rectangular pulse width is provided to the selection memory cell during a writing period. When the logic data is at a second logic level, the RESET pulse is provided to the selection memory cell and then a SET pulse larger than the reference write current and having the near-rectangular pulse width is provided to the selection memory cell during the writing period.

Abstract: A writing method for a resistive memory cell and a resistive memory are provided. The writing method includes following steps. A reference voltage is provided to a bit line of the resistive memory cell. A first voltage is provided to a word line of the resistive memory cell, and a second voltage is provided to a source line of the resistive memory cell, wherein the first voltage is not increased while the second voltage is progressively increased. Thus, when the writing method for the resistive memory cell is performed, the voltage of the word line is not increased while the voltage of the source line is progressively increased, so as to expand voltage window for reset operation. And, the chance for occurring the complementary switching manifestation of the resistive memory cell due to excessive input voltages is reduced.

Abstract: A resistive random access memory (RRAM) including a first electrode, a second electrode, and a variable-resistance oxide layer disposed between the first electrode and the second electrode is provided. The RRAM further includes an oxygen exchange layer, an oxygen-rich layer, and a first oxygen barrier layer. The oxygen exchange layer is disposed between the variable-resistance oxide layer and the second electrode. The oxygen-rich layer is disposed between the oxygen exchange layer and the second electrode. The first oxygen barrier layer is disposed between the oxygen exchange layer and the oxygen-rich layer.

Abstract: A resistive memory apparatus and a writing method thereof are provided. In the method, logic data is received, and a corresponding resistive memory cell is selected. A logic level of the logic data is determined. When the logic data is in a first logic level, where a first reading current of the corresponding resistive memory cell is greater than a first reference current, a set pulse and a reset pulse are provided to the resistive memory cell during a writing period. When the logic data is in a second logic level, where a second reading current of the resistive memory cell is smaller than a second reference current, the reset pulse is provided to the resistive memory cell during the writing period. Polarities of the reset pulse and the set pulse are opposite.

Abstract: A resistive memory apparatus and a reading method thereof are provided. In this method, two reading pulses are applied to a resistive memory cell, such that a first reading resistance and a second reading resistance of the resistive memory cell at different temperatures are sequentially obtained. Next, a resistive state of the second reading resistance is determined according to the reading resistances and the temperatures corresponding to the reading resistances. Thereafter, a logic level of storage data of the resistive memory cell is determined according to the resistive state of the second reading resistance.

Abstract: A resistive memory apparatus is provided. The resistive memory apparatus includes a plurality of memory cell pairs, and each of the memory cell pairs includes an active area, first and second word lines, a source line, first and second resistors and first and second bit lines. The active area is formed on a substrate, and the first and second word lines are formed on the substrate, and intersected with the active area. The source line is formed on the substrate and coupled to the active area. The first and second resistors are disposed on the substrate, and respectively coupled to the active area. The first and second bit lines are formed on the first and second resistors and coupled to the first and second resistors. The first and second bit lines are extended along a first direction which is substantially parallel to the first and second word lines.

Abstract: An imaging structure such as a mask or reticle may be fabricated using a patterning layer on an imaging layer. The patterning layer may have substantially different etch properties than the imaging layer. A first etch process may be selective of the patterning layer with respect to a resist layer. A second etch process may be selective of the imaging layer with respect to the patterning layer.

Abstract: Services of a multi-tier application can authorize (e.g., including authenticating) each other with one or more service access tokens provided by a security token service. In one implementation, an end-user can authenticate with the security token service to obtain one or more security tokens for communicating with an upstream application service. Requests that involve further processing from downstream services of the application can also involve service authorization/authentication measures. Thus, the upstream application service can also authenticate with the security token service to obtain one or more security tokens, such as a session token, and a service access token. The service access token for the upstream service can also include one or more signed policy settings. The upstream service can then use the one or more security tokens to prove authority to communicate with a downstream service in accordance with the policy settings.

Abstract: An imaging structure such as a mask or reticle may be fabricated using a patterning layer on an imaging layer. The patterning layer may have substantially different etch properties than the imaging layer. A first etch process may be selective of the patterning layer with respect to a resist layer. A second etch process may be selective of the imaging layer with respect to the patterning layer.

Abstract: An imaging structure such as a mask or reticle may be fabricated using a patterning layer on an imaging layer. The patterning layer may have substantially different etch properties than the imaging layer. A first etch process may be selective of the patterning layer with respect to a resist layer. A second etch process may be selective of the imaging layer with respect to the patterning layer.

Abstract: A cardiac restraint device includes a central cavity that receives the heart. A chamber surrounding the cavity presses against the surface of the heart when the chamber is filled with fluid. The inner wall defining the chamber is deformable, so that it tends to expand into the cavity and contact the heart. The outer wall of the chamber, or alternatively, a jacket surrounding the chamber, is nondeformable, so that expansive forces of the fluid in the chamber tend to be directed inward against the heart rather than outward.

Abstract: An imaging structure such as a mask or reticle may be fabricated using a patterning layer on an imaging layer. The patterning layer may have substantially different etch properties than the imaging layer. A first etch process may be selective of the patterning layer with respect to a resist layer. A second etch process may be selective of the imaging layer with respect to the patterning layer.

Abstract: An apparatus comprising a mask having an active device area and a moat. The moat substantially surrounds the mask active device area and has a width greater than a plasma specie diffusional length. A method comprising depositing a layer of resist on a mask substrate having transparent and opaque layers; and exposing the resist layer to radiation. The radiation is patterned to produce features within an active device area. The radiation is also patterned to produce a moat substantially surrounding the active device area having a width greater than a plasma specie diffusional length.

Abstract: An apparatus comprising a mask having an active device area and a moat. The moat substantially surrounds the mask active device area and has a width greater than a plasma specie diffusional length. A method comprising depositing a layer of resist on a mask substrate having transparent and opaque layers; and exposing the resist layer to radiation. The radiation is patterned to produce features within an active device area. The radiation is also patterned to produce a moat substantially surrounding the active device area having a width greater than a plasma specie diffusional length.

Abstract: An apparatus comprising a mask having an active device area and a moat. The moat substantially surrounds the mask active device area and has a width greater than a plasma specie diffusional length. A method comprising depositing a layer of resist on a mask substrate having transparent and opaque layers; and exposing the resist layer to radiation. The radiation is patterned to produce features within an active device area. The radiation is also patterned to produce a moat substantially surrounding the active device area having a width greater than a plasma specie diffusional length.