Patents by Inventor Fu-An Yu

Fu-An Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11126660
    Abstract: Large scale time series forecasting models are described that leverage deep learning. This can include the utilization of temporal convolution networks and long short-term memory (LTSM) units of recurrent neural networks (RNNS). The model architectures can handle very large data sets with a large number of time series. Diverse scaling is provided through use of a scale-free leveling network architecture, and sparse time-series data is managed using a gating approach. A deep temporally regularized matrix factorization approach to time-series forecasting is utilized that can leverage correlations between the time series during both training and prediction.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 21, 2021
    Assignee: A9.COM, INC.
    Inventors: Rajat Sen, Hsiang-Fu Yu, Inderjit Dhillon
  • Patent number: 11107899
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang
  • Patent number: 11088085
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu
  • Patent number: 11079801
    Abstract: An electronic device including a housing, a light source, and a printed pattern layer is provided. The housing includes an inner side and an outer side. The light source is disposed on the inner side of the housing. The printed pattern layer covers the outer side of the housing. The printed pattern layer includes a shielding area and a transparent area. A light beam from the light source transmits outward through the transparent area.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 3, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Fu-Yu Cai, Ming-Chih Huang, Tong-Shen Hsiung, Meng-Chu Huang, Shang-Chih Liang
  • Publication number: 20210225932
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
  • Publication number: 20210222857
    Abstract: A light-transmitting plastic casing and a manufacturing method thereof are provided. A manufacturing method of a light-transmitting plastic casing include the steps: providing a mixed material, the mixed material includes a resinous material, a flame retardant material, a transparent fiberglass material, and an elastomer material; performing a granulating step to the mixed material to form granules; performing a heating step to the granules; and performing a molding step to heated granules to form a light-transmitting plastic casing.
    Type: Application
    Filed: January 19, 2021
    Publication date: July 22, 2021
    Inventors: Li-Chen CHAN, Tong-Shen HSIUNG, Ming-Chih HUANG, Meng-Chu HUANG, Shang-Chih LIANG, Fu-Yu CAI, Chia-Hao HUNG
  • Publication number: 20210202708
    Abstract: A semiconductor device includes a substrate and a gate structure over the substrate. The semiconductor device includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well contacts at least two surfaces of the source. The semiconductor device further includes a second well having the first dopant type, wherein the second well contacts at least two surfaces of the drain. The semiconductor device further includes a deep well below the first well and below the second well, wherein the second well extends between the first well and the deep well. In some embodiments, the deep well has a second dopant type, and the second dopant type is opposite the first dopant type.
    Type: Application
    Filed: March 16, 2021
    Publication date: July 1, 2021
    Inventors: Chih-Chang CHENG, Fu-Yu CHU, Ruey-Hsin LIU
  • Publication number: 20210151666
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 20, 2021
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11011610
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang
  • Patent number: 11004897
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
    Type: Grant
    Filed: August 4, 2019
    Date of Patent: May 11, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
  • Publication number: 20210119115
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Application
    Filed: December 27, 2020
    Publication date: April 22, 2021
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Publication number: 20210088865
    Abstract: A method for fabricating an electrochromic device includes: depositing a first transparent film on a first substrate; depositing a first mesh structure on the first transparent film; depositing a second transparent film on the first mesh structure; depositing an electrochromic layer of WO3 or MoO3 on the second transparent film by an arc-plasma process to form a first electrode structure; depositing a third transparent film on a second substrate; depositing a second mesh structure on the third transparent film; depositing a fourth transparent film on the second mesh structure; forming an ion storage layer of PB on the fourth transparent film to produce a second electrode structure; binding the first and second electrode structures by having the electrochromic layer to face the ion storage layer; and, forming an electrolyte layer between the first and second electrode structures to produce the electrochromic device. In addition, an electrochromic device is also provided.
    Type: Application
    Filed: December 27, 2019
    Publication date: March 25, 2021
    Inventors: TIEN-FU KO, CHEN-TE CHANG, PO-WEN CHEN, HSIN-FU YU, KUO-CHUAN HO, SHENG-CHUAN HSU, JIN-YU WU, WEN-FA TSAI, HWEN-FEN HONG
  • Patent number: 10956521
    Abstract: Systems and methods presented herein create a graph of data within a data set, such as items within an electronic catalog. The nodes of the graph may represent data items, such as items within the electronic catalog. Links or edges can be created between nodes of the graph representative of a data-metric of interest. For example, links or edges can be created between nodes of the graph representative of co-access of items. A diversified page rank process can be performed with respect to a particular node in the graph. This process can use positive or negative bias toward specific attributes to dynamically re-weight edges before and/or during the walk.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: March 23, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Hsiang-Fu Yu, Ishwar Ramani
  • Patent number: 10957772
    Abstract: A semiconductor device includes a substrate and a gate structure over a top surface of the substrate. The semiconductor device further includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well surrounds the source. The semiconductor device further includes a second well having a second dopant type opposite the first dopant type, wherein the second well surrounds the drain, an entirety of an upper most surface of the second well between the drain and the first well is coplanar with the top surface of the substrate, and the second well is spaced from the first well.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu
  • Patent number: 10921861
    Abstract: An electronic device including a luminous strip is provided, including a housing, a first light guiding strip, a second light guiding strip, a light-transmissive structure, a first light-emitting element, a second light-emitting element and a third light-emitting element. The housing includes a first side wall and a second side wall, where a corner area exists between the first side wall and the second side wall. The first light guiding strip is disposed on the first side wall. The second light guiding strip is disposed on the second side wall. The light-transmissive structure is disposed in the corner area, and connected to the first light guiding strip and the second light guiding strip. The first light-emitting element is disposed at a first end of the first light guiding strip. The second light-emitting element is disposed at a second end of the second light guiding strip.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: February 16, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chieh Mii, Ming-Chih Huang, Tong-Shen Hsiung, Meng-Chu Huang, Fu-Yu Cai, Shang-Chih Liang, Chia-Hao Hung, Li-Wei Yu, Chi Cheng Liao, Hsin-I Lu, Cheng-Yu Lin
  • Patent number: 10916694
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Publication number: 20210005662
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
    Type: Application
    Filed: August 4, 2019
    Publication date: January 7, 2021
    Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
  • Publication number: 20200375040
    Abstract: An electronic device including a housing, a light source, and a printed pattern layer is provided. The housing includes an inner side and an outer side. The light source is disposed on the inner side of the housing. The printed pattern layer covers the outer side of the housing. The printed pattern layer includes a shielding area and a transparent area. A light beam from the light source transmits outward through the transparent area.
    Type: Application
    Filed: October 3, 2019
    Publication date: November 26, 2020
    Inventors: Fu-Yu CAI, Ming-Chih HUANG, Tong-Shen HSIUNG, Meng-Chu HUANG, Shang-Chih LIANG
  • Publication number: 20200343195
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 29, 2020
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu
  • Publication number: 20200333842
    Abstract: A casing of an electronic device including successive pattern structures is provided, including a first body, a second body, a first light emitting pattern, and a second light emitting pattern. The first body includes an outer surface and an inner surface, and the outer surface includes a first side edge. The second body includes an upper surface and a pivoting structure. The upper surface includes a covered area and an exposed area. The first body is pivotally connected to the second body through the pivoting structure, and the pivoting structure is located between the covered area and the exposed area. The first light emitting pattern is located on the outer surface and includes a first end extending to the first side edge. A second light emitting pattern, located on the exposed area, and including a second end. When the inner surface covers the covered area, the first end is aligned with the second end.
    Type: Application
    Filed: April 21, 2020
    Publication date: October 22, 2020
    Inventors: Meng-Chu HUANG, Chieh MII, Fu-Yu CAI, Chia-Hao HUNG, Shang-Chih LIANG, Ming-Chih HUANG, Tong-Shen HSIUNG