Patents by Inventor Fu Chu

Fu Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153943
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 9, 2024
    Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
  • Publication number: 20240145579
    Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Yun PENG, Fu-Ting YEN, Keng-Chu LIN
  • Patent number: 11970604
    Abstract: A germ-repellent plastic for use in a gas pathway of a respiratory device contains an anti-biofouling compound, and a basic plastic. The anti-biofouling compound is optionally selected from the group of a polyol, a polyether polyol, a polyol derivative, and a combination thereof; or the anti-biofouling compound is selected from the group consisting of a polyether, a poly(ethylene glycol) ether, a polysorbate, and a combination thereof; or the anti-biofouling compound is selected from the group consisting of poly(ethylene glycol) sorbitan monolaurate, poly(ethylene glycol) sorbitan monooleate, poly(ethylene glycol) sorbitol hexaoleate, ceteareth, and a combination thereof. The basic plastic is selected from the group of a blend of a low-density polyethylene polymer and an ethyl vinyl acetate copolymer, a blend of a polypropylene polymer and an ethyl vinyl acetate copolymer, a blend of polyolefin elastomer polymers and a polyvinyl chloride polymer.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 30, 2024
    Assignee: VINCENT MEDICAL MANUFACTURING CO., LTD.
    Inventors: Wenjun Meng, Sau Kuen Connie Kwok, Yueying Chen, Mingyu Zhang, Kwok Fu Fu, Ching Sau Chu
  • Publication number: 20240136438
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 25, 2024
    Inventors: Yu-Yun Peng, Fu-Ting Yen, Ting-Ting Chen, Keng-Chu Lin, Tsu-Hsiu Perng
  • Patent number: 11961834
    Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Jam-Wem Lee, Yu-Ti Su
  • Publication number: 20240120402
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.
    Type: Application
    Filed: November 19, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Chih-Hao WANG, Kuan-Lun CHENG
  • Publication number: 20240113195
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.
    Type: Application
    Filed: February 22, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Ni YU, Lung-Kun CHU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11942447
    Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Yang Chiou, Fu-Ting Yen, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240096994
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.
    Type: Application
    Filed: February 10, 2023
    Publication date: March 21, 2024
    Inventors: Lung-Kun CHU, Jia-Ni YU, Chun-Fu LU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11929363
    Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Jam-Wem Lee, Yu-Ti Su
  • Publication number: 20240072203
    Abstract: A method for fabricating light emitting diode (LED) dice includes the steps of: providing a substrate, and forming a plurality of die sized semiconductor structures on the substrate. The method also includes the steps of providing a receiving plate having an elastomeric polymer layer, placing the substrate and the receiving plate in physical contact with an adhesive force applied by the elastomeric polymer layer, and performing a laser lift-off (LLO) process by directing a uniform laser beam through the substrate to the semiconductor layer at an interface with the substrate to lift off the semiconductor structures onto the elastomeric polymer layer. During the laser lift-off (LLO) process the elastomeric polymer layer functions as a shock absorber to reduce momentum transfer, and as an adhesive surface to hold the semiconductor structures in place on the receiving plate.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicants: SemiLEDs Corporation, SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Chen-Fu Chu, Shih-Kai Chan, Yi-Feng Shih, David Trung Doan, Trung Tri Doan, Yoshinori Ogawa, Kohei Otake, Kazunori Kondo, Keiji Ohori, Taichi Kitagawa, Nobuaki Matsumoto, Toshiyuki Ozai, Shuhei Ueda
  • Patent number: 11916060
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
  • Publication number: 20240063339
    Abstract: A method for fabricating light emitting diode (LED) dice includes the steps of: providing a substrate, and forming a plurality of die sized semiconductor structures on the substrate. The method also includes the steps of providing a receiving plate having an elastomeric polymer layer, placing the substrate and the receiving plate in physical contact with an adhesive force applied by the elastomeric polymer layer, and performing a laser lift-off (LLO) process by directing a uniform laser beam through the substrate to the semiconductor layer at an interface with the substrate to lift off the semiconductor structures onto the elastomeric polymer layer. During the laser lift-off (LLO) process the elastomeric polymer layer functions as a shock absorber to reduce momentum transfer, and as an adhesive surface to hold the semiconductor structures in place on the receiving plate.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 22, 2024
    Applicants: SamiLEDs Corporation, SHIN-ETSU CHEMICAL. CO., LTD.
    Inventors: Chen-Fu Chu, SHIH-KAI CHAN, YI-FENG SHIH, DAVID TRUNG DOAN, TRUNG TRI DOAN, YOSHINORI OGAWA, KOHEI OTAKE, KAZUNORI KONDO, KEIJI OHORI, TAICHI KITAGAWA, NOBUAKI MATSUMOTO, TOSHIYUKI oZAI, SHUHEI UEDA
  • Patent number: 11862754
    Abstract: A method for fabricating light emitting diode (LED) dice includes the steps of: providing a substrate, and forming a plurality of die sized semiconductor structures on the substrate. The method also includes the steps of providing a receiving plate having an elastomeric polymer layer, placing the substrate and the receiving plate in physical contact with an adhesive force applied by the elastomeric polymer layer, and performing a laser lift-off (LLO) process by directing a uniform laser beam through the substrate to the semiconductor layer at an interface with the substrate to lift off the semiconductor structures onto the elastomeric polymer layer. During the laser lift-off (LLO) process the elastomeric polymer layer functions as a shock absorber to reduce momentum transfer, and as an adhesive surface to hold the semiconductor structures in place on the receiving plate.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: January 2, 2024
    Assignees: SemiLEDs Corporation, Shin-Etsu Chemical Co., Ltd.
    Inventors: Chen-Fu Chu, Shih-Kai Chan, Yi-Feng Shih, David Trung Doan, Trung Tri Doan, Yoshinori Ogawa, Kohei Otake, Kazunori Kondo, Keiji Ohori, Taichi Kitagawa, Nobuaki Matsumoto, Toshiyuki Ozai, Shuhei Ueda
  • Patent number: 11862755
    Abstract: A method for fabricating light emitting diode (LED) dice includes the steps of: providing a substrate, and forming a plurality of die sized semiconductor structures on the substrate. The method also includes the steps of providing a receiving plate having an elastomeric polymer layer, placing the substrate and the receiving plate in physical contact with an adhesive force applied by the elastomeric polymer layer, and performing a laser lift-off (LLO) process by directing a uniform laser beam through the substrate to the semiconductor layer at an interface with the substrate to lift off the semiconductor structures onto the elastomeric polymer layer. During the laser lift-off (LLO) process the elastomeric polymer layer functions as a shock absorber to reduce momentum transfer, and as an adhesive surface to hold the semiconductor structures in place on the receiving plate.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: January 2, 2024
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Chen-Fu Chu, Shih-Kai Chan, Yi-Feng Shih, David Trung Doan, Trung Tri Doan, Yoshinori Ogawa, Kohei Otake, Kazunori Kondo, Keiji Ohori, Taichi Kitagawa, Nobuaki Matsumoto, Toshiyuki Ozai, Shuhei Ueda
  • Publication number: 20230400967
    Abstract: A method for providing dynamic in-context information is disclosed.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Applicant: MicroStrategy Incorporated
    Inventors: Keng-Fu CHU, Amy LARESCH, Yung-Sheng CHEN, Zhili CHENG, Alejandro Olvera VELASCO, Jaime PEREZ
  • Publication number: 20230274072
    Abstract: A method includes identifying a cell in the layout diagram as a violated cell that fails to pass one or more design rules related to IR drops, and classifying a root cause of the violated cell with a root cause class. The method also includes determining a searching area for searching safe region candidates, and finding a selected cell for moving based upon the root cause class of the root cause. The method further includes finding a safe region in the searching area for moving the selected cell, and moving the selected cell to the safe region if the safe region is found within the searching area.
    Type: Application
    Filed: March 10, 2022
    Publication date: August 31, 2023
    Inventors: Fa ZHOU, JinXin LIU, Chieh-Fu CHU, Yen-Feng SU, Chia-Chun LIAO, Meng-Hsuan WU, Dei-Pei LIU
  • Publication number: 20230178697
    Abstract: A packaged LED device comprising: a pad-extended LED chip comprising: at least one LED chip having a substrate, a first semiconductor layer, an active layer and a second semiconductor layer; a first pad electrically connected to the first type semiconductor layer and a second pad electrically connected to the second type semiconductor layer; and a first extended metal layer connected to the first pad and a second extended metal layer connected to the second pad.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Inventors: Chen-Fu CHU, Trung Tri Doan
  • Patent number: 11645445
    Abstract: Disclosed are methods, systems, and computer-readable medium for dynamically displaying database containers. A container including content and a minimum display size for the document may be received. The display size of the document may be monitored. A determination that the display size of the document is less than the minimum display size may be made. A visible section and a hidden section of the document may be determined based on the display size. The visible section of the document may be displayed. A scroll feature may be activated based on a hidden section size. An indication to scroll the document in a scroll direction may be received. The visible section may be updated to an updated visible section that includes at least a portion of the hidden section. The updated visible section of the document may be displayed via the display.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: May 9, 2023
    Assignee: MICROSTRATEGY INCORPORATED
    Inventors: Alejandro Olvera Velasco, Chuanhao Ma, Amy Dina Laresch, Keng-Fu Chu, Zhili Cheng
  • Publication number: 20230116811
    Abstract: The present invention relates to a fiber-containing structure comprising an interwoven and welded base material and a welded elastomer layer, and at least one part of the base material and the welded elastomer layer are welded to each other. The invention also relates to a method for manufacturing the fiber-containing structure and a shoe structure containing the fiber-containing structure.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: CHIH-YI LIN, CHUNG-CHIH FENG, KAO-LUNG YANG, KO-FU CHU