Patents by Inventor Fu Lin

Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12366563
    Abstract: A method of identifying a location of pathogens in a structure including monitoring air within the structure for pathogens to set a baseline level, detecting a rise in pathogen density with respect to the baseline level, at least partially closing at least a first zone of the system, monitoring air from a second zone for a change in relative pathogen density to the previously detected pathogen density, and toggling the first zone and the second zone based on the change in relative pathogen density.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: July 22, 2025
    Assignee: HAMILTON SUNDSTRAND CORPORATION
    Inventors: Fu Lin, Russell Taylor, Daniel A. Mosher
  • Publication number: 20250218902
    Abstract: A semiconductor structure includes a bottom wafer having a bottom substrate and a bottom interconnect structure on the bottom substrate, and a top wafer having a top substrate with a front surface and a rear surface and a top interconnect structure disposed on the front surface of the top substrate. The top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer. An oxide-nitride-oxide (ONO) dielectric layer covers the rear surface of the top substrate. A plurality of conductive vias is disposed on the rear surface and extending into the ONO dielectric layer and the top substrate.
    Type: Application
    Filed: January 26, 2024
    Publication date: July 3, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chu-Fu Lin, Chuan-Lan Lin, Yu-Ping Wang, Chun-Hung Chen
  • Publication number: 20250183191
    Abstract: A fan-out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.
    Type: Application
    Filed: January 24, 2025
    Publication date: June 5, 2025
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Patent number: 12313544
    Abstract: A method and device for identifying the washing quality of a feather material are applied to a feather material washing apparatus and essentially entail: a sampling unit that takes an appropriate amount of the water discharged from the feather material washing apparatus as a water sample, an impurity removing module that removes feather fiber and impurities that may compromise inspection accuracy, and a laser sensing device that senses, while the water sample is static, a transparency value of a portion of the water sample that extends across a predetermined distance, in order to identify the washing quality of a washed feather material. The method and device for identifying the washing quality of a feather material exercise intelligent judgment to enable a consistent standard, to ensure the efficiency and quality of a feather material washing procedure, and to reduce the associated costs.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 27, 2025
    Assignee: KWONG LUNG ENTERPRISE CO., LTD.
    Inventors: Jui-Wen Wang, Yuan-Fu Lin, Chun-Hao Miao, Wei-Lun Lan, Che-Wei Chien
  • Publication number: 20250166997
    Abstract: The invention provide an edge structure of a semiconductor wafer, which comprise a first substrate, an edge region and a device region are defined on that first substrate, a first material layer covers a first surface and a side surface of the edge region, and a second material layer covers the first material layer, the cross-sectional structure of the second material layer gradually decreases from the device region to the edge region.
    Type: Application
    Filed: December 13, 2023
    Publication date: May 22, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ping Wang, Chuan-Lan Lin, Chu-Fu Lin, Teng-Chuan Hu, Kun-Ju Li
  • Patent number: 12283779
    Abstract: A high-speed connector includes an insulating housing, a first terminal assembly received in the insulating housing, a second terminal assembly received in the insulating housing, a third terminal assembly received in the insulating housing, and a fourth terminal assembly received in the insulating housing. The second terminal assembly is opposite to the first terminal assembly along an up-down direction. The third terminal assembly is disposed between the first terminal assembly and the second terminal assembly. The fourth terminal assembly is corresponding to the third terminal assembly. The fourth terminal assembly is disposed between the second terminal assembly and the third terminal assembly.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: April 22, 2025
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Yun-Chien Lee, Yi-Ching Hsu, Pei-Yi Lin, Yu-Hung Su, Sheng-Yuan Huang, Chun-Fu Lin
  • Patent number: 12278189
    Abstract: An electronic package is provided, in which a circuit board and a circuit block are embedded in an encapsulating layer at a distance to each other, and circuit structures are formed on the two opposite surfaces of the encapsulating layer with electronic components arranged on one of the circuit structures. The circuit block and the circuit board embedded in the encapsulating layer are spaced apart from each other to allow to separate current conduction paths. As such, the circuit board will not overheat, and issues associated with warpage of the circuit board can be eliminated. Moreover, by embedding the circuit block and the circuit board in the encapsulating layer at a distance to each other, the structural strength of the encapsulating layer can be improved.
    Type: Grant
    Filed: October 4, 2023
    Date of Patent: April 15, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chih-Ming Huang, Kuo-Hua Yu, Chang-Fu Lin
  • Patent number: 12276923
    Abstract: An exhaust system for discharging from semiconductor manufacturing equipment a hazardous gas includes: a main exhaust pipe above the semiconductor manufacturing equipment and having a top surface on a first side and a bottom surface on a second side, a first branch pipe connected to a source of a gas mixture containing the hazardous gas on the second side and connected to the main exhaust pipe through the top surface, a second branch pipe connected to a gas box on the second side and connected to the main exhaust pipe through the bottom surface, and a detector on the second branch pipe configured to detect presence of the hazardous gas and downstream to the gas box. The first and the second branch pipes are connected to the main exhaust pipe at a first location and a second location, respectively. The first location is more upstream than the second location.
    Type: Grant
    Filed: May 24, 2024
    Date of Patent: April 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Fu Lin, Shih-Chang Shih, Chia-Chen Chen
  • Publication number: 20250116603
    Abstract: A method and device for identifying the washing quality of a feather material are applied to a feather material washing apparatus and essentially entail: a sampling unit that takes an appropriate amount of the water discharged from the feather material washing apparatus as a water sample, an impurity removing module that removes feather fiber and impurities that may compromise inspection accuracy, and a laser sensing device that senses, while the water sample is static, a transparency value of a portion of the water sample that extends across a predetermined distance, in order to identify the washing quality of a washed feather material. The method and device for identifying the washing quality of a feather material exercise intelligent judgment to enable a consistent standard, to ensure the efficiency and quality of a feather material washing procedure, and to reduce the associated costs.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Applicant: KWONG LUNG ENTERPRISE CO., LTD.
    Inventors: Jui-Wen WANG, Yuan-Fu LIN, Chun-Hao MIAO, Wei-Lun LAN, Che-Wei CHIEN
  • Publication number: 20250106961
    Abstract: According to an embodiment of the invention, a backlight driver of driving a light-emitting diode (LED) string via a driving transistor in a load path is provided. The LED string, the driving transistor, and an electrical load are coupled to form the load path. The backlight driver includes a current regulator and a headroom detection circuit. The current regulator is coupled to the driving transistor and the first terminal of the electrical load to control a driving current flowing through the load path according to at least a feedback voltage from a first terminal of the electrical load. The headroom detection circuit is coupled to the first terminal of the electrical load and a voltage regulator to control the voltage regulator to regulate a supply voltage to a first terminal of the LED string according to at least the feedback voltage.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Applicant: NOVATEK Microelectronics Corp.
    Inventors: Jhih-Siou Cheng, Keko-Chun Liang, Chun-Fu Lin, Jin-Yi Lin, Chieh-An Lin, Po-Hsiang Fang
  • Publication number: 20250096522
    Abstract: An optoelectronic device includes a first substrate, a second substrate, a photonic integrated circuit, and a laser diode. The second substrate is over the first substrate. The photonic integrated circuit is disposed on the first substrate and includes a first waveguide channel, a second waveguide channel, and a patterned structure. The first waveguide channel and the second waveguide channel are coupled to the patterned structure. The laser diode is disposed on the second substrate and configured to emit a light beam toward the patterned structure.
    Type: Application
    Filed: September 19, 2024
    Publication date: March 20, 2025
    Applicant: AuthenX Inc.
    Inventors: Sheng-Fu LIN, Po-Kuan SHEN, Yi-Ting LU, Chu-Ching TSAI, Jenq-Yang CHANG, Mao-Jen WU
  • Publication number: 20250097637
    Abstract: Circuit, method for audio signal processing with excursion estimation compensation, and non-transitory storage medium are provided. The circuit comprises a delay circuit, compensation filter, excursion estimator, peak detector, gain determination circuit, and gain adjustment circuit. The delay circuit is for delaying a digital audio signal to output a delayed digital audio signal. The compensation filter is for generating a compensated digital audio signal according to the digital audio signal for excursion estimation compensation for a speaker type. The excursion estimator is for determining an estimated excursion signal for the speaker type according to the compensated digital audio signal. The gain determination circuit is for generating a gain setting signal according to the estimated excursion signal and a threshold value. The gain adjustment circuit is for generating an adjusted digital audio signal according to the gain setting signal and delayed digital audio signal.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 20, 2025
    Inventors: HSIN-YUAN CHIU, TSUNG-FU LIN, WUN-LONG YU
  • Patent number: 12255182
    Abstract: An electronic package is provided, in which a first electronic element and a second electronic element are disposed on a first side of a circuit structure and a second side of the circuit structure, respectively, where a first metal layer is formed between the first side of the circuit structure and the first electronic element, a second metal layer is formed on a surface of the second electronic element, and at least one thermally conductive pillar is disposed on the second side of the circuit structure and extends into the circuit structure to thermally conduct the first metal layer and the second metal layer. Therefore, through the thermally conductive pillar, heat generated during operations of the first electronic element and the second electronic element can be quickly dissipated to an external environment and would not accumulate.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: March 18, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Meng-Huan Chia, Yih-Jenn Jiang, Chang-Fu Lin, Don-Son Jiang
  • Patent number: 12255165
    Abstract: An electronic package is provided and includes a carrier for carrying electronic components. Electrical contact pads of the carrier for planting solder balls are connected with a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion in the carrier. By connecting a plurality of conductors with a single electrical contact pad, structural stress can be distributed and breakage of the circuit portion can be prevented.
    Type: Grant
    Filed: March 12, 2024
    Date of Patent: March 18, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ren Chen, Po-Yung Chang, Pei-Geng Weng, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
  • Patent number: 12255421
    Abstract: A connector lock structure includes an insulating body, a plurality of terminals, a shell, a locking assembly, a sliding board, a pressing element and an unlocking tool. The insulating body is molded around the plurality of the terminals. The shell surrounds the insulating body. The locking assembly includes at least one lacking groove, and at least one elastic arm formed in the at least one lacking groove. The at least one elastic arm has a hook structure. The hook structure is cooperated with a blocking groove of a docking connector. The pressing element is mounted in the insulating body. The sliding board is slidably mounted under the pressing element. One end of the pressing element has a locking portion. The locking portion has a keyhole. The unlocking tool is inserted in the keyhole.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: March 18, 2025
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Li Nien Hsu, Sheng Nan Yu, Chun Fu Lin
  • Patent number: 12249796
    Abstract: An electrical connector includes an insulating body, a plurality of conductive terminals, a plurality of grounding terminals and two shielding elements. The plurality of the conductive terminals are mounted in the insulating body. The plurality of the grounding terminals are mounted in the insulating body. The plurality of the grounding terminals are located adjacent to two outer sides of the plurality of the conductive terminals. The two shielding elements are disposed at a front end of an upper surface and a front end of a lower surface of the insulating body. Each shielding element has a base frame. Two sides of a rear edge of the base frame are connected with two contact portions. The contact portions of the two shielding elements contact with the plurality of the grounding terminals.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: March 11, 2025
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Pei-Yi Lin, Chuan-Hung Lin, Sheng-Nan Yu, Sheng-Yuan Huang, Chun-Fu Lin
  • Patent number: 12246472
    Abstract: Provided is a mold core structure, which is arranged on a mold.
    Type: Grant
    Filed: May 19, 2024
    Date of Patent: March 11, 2025
    Inventors: Shun Fu Lin, Yu-Chang Su
  • Patent number: 12248647
    Abstract: A touch panel includes a substrate, a plurality of control signal lines, a plurality of first reading signal lines, and a plurality of second reading signal lines. The plurality of control signal lines are disposed on a first surface of the substrate and spaced from each other. The plurality of first reading signal lines are disposed on a second surface of the substrate and spaced from each other. The second surface is opposite to the first surface. The plurality of second reading signal lines are disposed on the first surface of the substrate. Each of the plurality of second reading signal lines is located between adjacent two of the plurality of control signal lines. An electronic device including the above touch panel is also provided.
    Type: Grant
    Filed: November 8, 2023
    Date of Patent: March 11, 2025
    Assignee: E Ink Holdings Inc.
    Inventor: Chun-Fu Lin
  • Publication number: 20250076369
    Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.
    Type: Application
    Filed: April 16, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ronald Kuo-Hua Ho, Kun-Yu Wang, Yen-Chang Shih, Sung-Te Chen, Cheng-Han Wu, Yi-Ying Liao, Chun-Ming Huang, Yen-Feng Lu, Ching-Yu Tsai, Tai-Lai Tung, Kuan-Fu Lin, Bo-Kang Lai, Yao-Syuan Lee, Tsyr-Rou Lin, Ming-Chao Tsai, Li-Hsuan Chiu
  • Patent number: 12243472
    Abstract: A light-emitting diode (LED) panel and a driving device therefore is provided. The driving device includes a source driver and a scan driver. The source driver is coupled to a plurality of data lines disposed in the LED panel. The source driver outputs driving currents to the data lines in any one of a plurality of scan line periods, to drive an LED array of the LED panel. The scan driver is coupled to a plurality of scan lines disposed in the LED panel, wherein the scan driver scans the scan lines during the plurality of scan line periods. In an active period of any one of the scan line periods, the scan driver applies an enable voltage to a current scan line among the scan lines, and the scan driver applies a pre-charge voltage to other scan line among the scan lines.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: March 4, 2025
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yu-Sheng Ma, Jhih-Siou Cheng, Chun-Fu Lin, Jin-Yi Lin