Patents by Inventor Fu Lin
Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12218189Abstract: A semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. A method for manufacturing a semiconductor device and a method for reducing an influence of a dielectric film are also disclosed.Type: GrantFiled: November 24, 2023Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Fu Lin, Tsung-Hao Yeh, Chih-Wei Hung
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Patent number: 12199212Abstract: A method for transferring light emitting elements during manufacture of a display panel includes providing light emitting elements; providing a first electromagnetic plate defining adsorption positions; providing a receiving substrate defining receiving areas; energizing the first electromagnetic plate to magnetically adsorb one of the light emitting elements at each adsorption position; facing the first electromagnetic plate to the receiving substrate; and transferring the light emitting elements to one corresponding receiving area of the receiving substrate.Type: GrantFiled: March 22, 2022Date of Patent: January 14, 2025Assignee: Century Technology (Shenzhen) Corporation LimitedInventors: Po-Liang Chen, Yung-Fu Lin
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Publication number: 20250010294Abstract: A method for performing continuous single molecule nucleic acids sequencing is provided. The method includes the following operations. A sequencing chip is placed on a detection module configured to detect a plurality of fluorescent lights having different wavelengths. Each of the plurality of fluorescent lights is generated from one of a plurality of single-molecule nucleic acids of a sample on the sequencing chip, the detection module comprises at least one sensor device, each of the at least one sensor device having a plurality of pixels. In operating the detection module, an objective lens is used to collect one of the plurality of fluorescent lights; and a projective lens is used to concentrate the one of the fluorescent lights to project a spot on the at least one sensor device. A projected spot size of the spot is smaller than or equal to 1.5 times a size of the pixel.Type: ApplicationFiled: September 18, 2024Publication date: January 9, 2025Inventors: Chung-Fan CHIOU, Kuang-Po CHANG, Chi-Fu YEN, Sheng-Fu LIN
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Publication number: 20250011594Abstract: A resin composition is disclosed. The resin composition includes 100 parts by weight of vinyl group-containing polyphenylene ether, 20 parts by weight to 60 parts by weight of ethylene-styrene-divinylbenzene copolymer, and 5 parts by weight to 15 parts by weight of a compound represented by the Formula (1). An article made from the composition is also disclosed, and the article includes prepreg, resin film, laminate, or printed circuit board.Type: ApplicationFiled: August 9, 2023Publication date: January 9, 2025Applicant: ELITE MATERIAL CO., LTD.Inventors: Shu-Hao CHANG, Yueh-Fu LIN
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Patent number: 12190793Abstract: The present disclosure relates to a driver for driving a light emitting unit array of a display device, the driver including: a plurality of driving units, each of the plurality of driving units includes: a driving circuit configured to provide a driving current to a corresponding column of light emitting units in the light emitting unit array according to a pulse width modulation signal, during a turn-on period of a channel switch; a charge path circuit configured to be connected in parallel with the driving circuit, and to be turned on during the turn-on period of the channel switch to form a charge path; and a discharge path circuit configured to be connected in parallel with the driving circuit, and to be turned-on after the channel switch is turned off, to form a discharge path.Type: GrantFiled: June 2, 2023Date of Patent: January 7, 2025Assignee: NOVATEK MICROELECTRONICS CORP.Inventors: Yu-Sheng Ma, Jhih-Siou Cheng, Chun-Fu Lin, Jin-Yi Lin, Ju-Lin Huang
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Publication number: 20240429093Abstract: A method for fabricating a semiconductor device includes the steps of first defining a scribe line on a front side of a wafer, in which the wafer includes an inter-metal dielectric (IMD) layer disposed on a substrate and an alternating stack disposed on the IMD layer. Next, part of the alternating stack is removed to form a trench on the front side of the wafer, a dielectric layer is formed in the trench, and then a dicing process is performed along the scribe line from a back side of the wafer to divide the wafer into chips.Type: ApplicationFiled: July 21, 2023Publication date: December 26, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Ting Lin, Kai-Kuang Ho, Chuan-Lan Lin, Yu-Ping Wang, Chu-Fu Lin, Yi-Feng Hsu, Yu-Jie Lin
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Patent number: 12173744Abstract: A thumb screw includes a main body and a rotating member. The main body has a shank and a threaded portion which are connected together along an axis of the main body. The shank has a groove and two guiding holes respectively located on two opposite sides of the groove and communicating with the groove. The rotating member has a head, a rod connected to an end surface of the head, and two pin portions connected to the rod. The head has two receiving grooves adapted to receive two partial end portions of the shank. When the two partial end portions leave the two receiving grooves and the two pin portions are respectively located in the two guiding holes, the rotating member could pivot around the two pin portions relative to the main body, thereby allowing the thumb screw to be received.Type: GrantFiled: December 29, 2022Date of Patent: December 24, 2024Assignee: ACCTON TECHNOLOGY CORPORATIONInventor: Jyun-Fu Lin
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Patent number: 12176327Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: GrantFiled: April 28, 2023Date of Patent: December 24, 2024Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
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Publication number: 20240379486Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. A semiconductor device is disposed on the substrate. An interlayer dielectric (ILD) structure is disposed over the substrate and the semiconductor device. A first intermetal dielectric (IMD) structure is disposed over the substrate and the ILD structure. An opening is disposed in the first IMD structure. The opening overlies at least a portion of the semiconductor device.Type: ApplicationFiled: July 19, 2024Publication date: November 14, 2024Inventors: Harry-Hak-Lay Chuang, Hsin Fu Lin, Shiang-Hung Huang, Tsung-Hao Yeh
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Publication number: 20240371884Abstract: In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.Type: ApplicationFiled: July 18, 2024Publication date: November 7, 2024Inventors: Harry-Hak-Lay Chuang, Wen-Tuo Huang, Hsin Fu Lin, Wei Cheng Wu
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Publication number: 20240371695Abstract: A method for fabricating a semiconductor device includes the steps of first providing a wafer, forming a scribe line on a front side of the wafer, performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely, performing a laminating process to form a tape on the front side of the wafer, performing a grinding process on a backside of the wafer, and then performing an expanding process to divide the wafer into chips.Type: ApplicationFiled: June 1, 2023Publication date: November 7, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo
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Publication number: 20240371987Abstract: A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.Type: ApplicationFiled: July 18, 2024Publication date: November 7, 2024Inventors: Chi-Fu LIN, Cheng-Hsin CHEN, Ming-I HSU, Kun-Ming HUANG, Chien-Li KUO
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Patent number: 12136379Abstract: A display panel includes a plurality of driving electrode regions and a plurality of wiring regions connected between the driving electrode regions. A (2n?1)th wiring region extended from a (2n?1)th driving electrode region toward a (2n)th driving electrode region has a wiring extending direction forming a first included angle with an arrangement direction, and a (2n)th wiring region extended from the (2n)th driving electrode region toward a (2n+1)th driving electrode region has a wiring extending direction forming a second included angle with the arrangement direction, and a (2n+1)th wiring region extended from the (2n+1)th driving electrode region toward a (2n+2)th driving electrode region has a wiring extending direction forming a third included angle with the arrangement direction, wherein n is a positive integer. At least one of the first included angle, the second included angle and the third included angle is positive and at least one of them is negative.Type: GrantFiled: July 10, 2023Date of Patent: November 5, 2024Assignee: AUO CorporationInventors: Chun-Yu Lin, Kun-Cheng Tien, Jia-Long Wu, Rong-Fu Lin, Shu-Hao Huang
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Patent number: 12136627Abstract: In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.Type: GrantFiled: January 11, 2022Date of Patent: November 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Wen-Tuo Huang, Hsin Fu Lin, Wei Cheng Wu
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Publication number: 20240347630Abstract: A semiconductor device includes a semiconductor layer, a drift region, a source area, a well region, a drain area, and a dielectric film. The drift region and the source area are formed in the semiconductor layer. The well region is formed in the semiconductor layer and between the drift region and the source area. The drain area is formed in the drift region. The dielectric film is formed in the drift region and is located between the source area and the drain area. The dielectric film includes a proximate end portion and a distal end portion which are proximate to and distal from the source area, respectively, and which are asymmetrical to each other.Type: ApplicationFiled: June 27, 2024Publication date: October 17, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Fu LIN, Chien-Hung LIU, Tsung-Hao YEH
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Publication number: 20240335982Abstract: Provided is a mold with a variotherm mold temperature structure, including a based body, a heating device and an air control device. A mold cavity and a hot runner are provided inside the base body. The inside of the hot runner is filled with a working fluid, and the temperature and circulation of the working fluid are maintained by the heating device. A cold gas runner is provided between the hot runner and the mold cavity, and a plurality of brackets are arranged inside the cold gas runner. The air control device is communicated with one end of the cold gas runner, and can inject medium and low temperature gas from one end of the cold gas runner such that the medium and low temperature gas exchanges temperature with the base body.Type: ApplicationFiled: May 11, 2023Publication date: October 10, 2024Inventors: Shun-Fu Lin, Chun-Jen Chen
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Publication number: 20240332351Abstract: A capacitor structure comprises a substrate having a first side and a second side opposite to the first side; a plurality of first trenches formed on the first side of the substrate; a plurality of second trenches formed on the second side of the substrate; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches, wherein a first depth of each of the first trenches or a second depth of each of the second trenches is greater than half of a thickness of the substrate.Type: ApplicationFiled: June 14, 2024Publication date: October 3, 2024Inventors: Teng-Chuan HU, Chu-Fu LIN, Chun-Hung CHEN
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Patent number: 12103072Abstract: The invention provides a composite particle material for selective laser sintering (SLS), which is composed of an inorganic powder coated with a binder. The composite particulate material is formed by mixing the inorganic powder and the binder to have the binder directly coated on the outer surface of the inorganic powder. In addition, the inorganic powder to be coated by the binder is preferably using a powder having a smaller particle size and a larger particle size distribution, and thereby the production cost can be greatly reduced. Further, since the outer surface of the inorganic powder is coated with the binder, there are no problems such as causing oxidation of the inorganic powder and so on. Furthermore, manufacturing the composite particle material can be easily carried out in a general ambient or an atmospheric environment, and the powder material after use is recyclable.Type: GrantFiled: January 16, 2023Date of Patent: October 1, 2024Assignee: National Taiwan University of Science and TechnologyInventors: Yu-Deh Chao, Shu-Cheng Liu, Jeng-Ywan Jeng, Fu-Lin Chen
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Patent number: 12107333Abstract: This invention provides an antenna assembly equipped with a sub-wavelength structured enhancer, comprising an antenna supporting substrate with a top surface and a bottom surface opposite to each other; a first patch antenna is disposed on the top surface of the antenna supporting substrate or inside of the antenna supporting substrate; a ground layer is disposed under the bottom surface of the antenna supporting substrate; a signal feeding layer for transmitting satellite communicating signals is disposed on one of surfaces of the antenna supporting substrate, or inside of the antenna supporting substrate, or under the first patch antenna, or under a side of the ground layer back to the antenna supporting substrate; and a solid sub-wavelength structured enhancer is disposed above the first patch antenna and spaced with each other by an air gap ranging between 7 mm and 47 mm.Type: GrantFiled: September 14, 2022Date of Patent: October 1, 2024Assignee: AuthenX Inc.Inventors: Yu-Chun Wang, Po-Kuan Shen, Sheng-Fu Lin, Jenq-Yang Chang, Mao-Jen Wu
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Publication number: 20240321798Abstract: An electronic package is provided and includes a carrier for carrying electronic components. Electrical contact pads of the carrier for planting solder balls are connected with a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion in the carrier. By connecting a plurality of conductors with a single electrical contact pad, structural stress can be distributed and breakage of the circuit portion can be prevented.Type: ApplicationFiled: March 12, 2024Publication date: September 26, 2024Applicant: SILICONWARE PRECISION INDUST RIES CO., LT D.Inventors: Chi-Ren Chen, Po-Yung Chang, Pei-Geng Weng, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang