Abstract: A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.

Abstract: An electronic package is provided and includes an electronic element, an intermediary structure disposed on the electronic element, and a heat dissipation element bonded to the electronic element through the intermediary structure. The intermediary structure has a flow guide portion and a permanent fluid combined with the flow guide portion so as to be in contact with the electronic element, thereby achieving a preferred heat dissipation effect and preventing excessive warping of the electronic element or the heat dissipation element due to stress concentration.

Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.

Abstract: An exhaust system for discharging from semiconductor manufacturing equipment a hazardous gas includes: a main exhaust pipe above the semiconductor manufacturing equipment and having a top surface on a first side and a bottom surface on a second side, a first branch pipe connected to a source of a gas mixture containing the hazardous gas on the second side and connected to the main exhaust pipe through the top surface, a second branch pipe connected to a gas box on the second side and connected to the main exhaust pipe through the bottom surface, and a detector on the second branch pipe configured to detect presence of the hazardous gas and downstream to the gas box. The first and the second branch pipes are connected to the main exhaust pipe at a first location and a second location, respectively. The first location is more upstream than the second location.

Abstract: Provided is a mold core structure, which is arranged on a mold.

Abstract: A heat dissipation structure is provided and includes a heat dissipation body and an adjustment channel. A carrying area and an active area adjacent to the carrying area are defined on a surface of the heat dissipation body, the carrying area is used for applying a first heat dissipation material thereonto, and the adjustment channel is formed in the active area, where one end of the adjustment channel communicates with the outside of the heat dissipation structure, and the other end communicates with the carrying area. Therefore, when the heat dissipation body is coupled to the electronic component by the first heat dissipation material, the adjustment channel can adjust a volume of the first heat dissipation material.

Abstract: Provided are device with stepped isolation regions and methods for fabricating the same. An exemplary method includes forming mask segments over a semiconductor material; etching the semiconductor material to form first trenches, wherein the first trenches have a first trench maximum width and a first trench depth; forming a coating in the first trenches, wherein the coating has a coating depth less than the first trench depth, and wherein uncovered portions of the semiconductor material extend from the coating to the patterned masks; performing an etch process to etch the mask segments and the uncovered portions of the semiconductor material to form second trenches over the first trenches, wherein the second trenches have a second minimum width greater than the first maximum width and a second depth less than the first depth; and removing the coating from the first trenches.

Abstract: A field effect transistor includes a source-side doped well, a drift-region well, a source region, a drain region; a shallow trench isolation structure including a first portion overlying the drift-region well and laterally spaced from the source-side doped well; a gate dielectric layer; a gate electrode overlying the gate dielectric layer; and a proximal doped layer stack embedded within the drift-region well and interposed between the source-side doped well and the first portion of the shallow trench isolation structure. Proximal doped semiconductor layers of the proximal doped layer stack have different average atomic concentrations of dopants of the second conductivity type.

Abstract: A source driver and a driving system for driving an LED panel, and an LED display system are provided. The driving system includes: a plurality of source drivers, for respectively supplying driving currents to channels of different portions on the LED panel, and each source driver includes: a plurality of driving circuits, which are in one-to-one correspondence with the plurality of channels on the LED panel, and are connected to a same current control line, each driving circuit being configured to supply a driving current to a corresponding channel, wherein, the supplied driving current is associated with a voltage on the current control line which the driving circuit is connected with. When one or more driving circuits switch between a non-driving state and a driving state, the driving current being supplied by the driving circuit(s) being in the driving state in the plurality of source drivers is compensated.

Abstract: A fan-out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

Abstract: A semiconductor device includes a semiconductor layer, a drift region, a source area, a well region, a drain area, and a dielectric film. The drift region and the source area are formed in the semiconductor layer. The well region is formed in the semiconductor layer and between the drift region and the source area. The drain area is formed in the drift region. The dielectric film is formed in the drift region and is located between the source area and the drain area. The dielectric film includes a proximate end portion and a distal end portion which are proximate to and distal from the source area, respectively, and which are asymmetrical to each other.

Abstract: A circuit board with improved heat dissipation function and a method for manufacturing the circuit board are provided. The method includes providing a first metal layer defining a first slot; forming a first adhesive layer in the first slot; electroplating copper on each first pillar to form a first heat conducting portion; forming a first insulating layer on the first adhesive layer having the first heat conducting portion, and defining a first blind hole in the first insulating layer; filling the first blind hole with thermoelectric separation metal to form a second heat conducting portion; forming a first wiring layer on the first insulating layer; forming a second insulating layer on the first wiring layer, defining a second blind hole on the second insulating layer; electroplating copper in the second blind hole to form a third heat conducting portion; mounting an electronic component on the second insulating layer.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: An integrated circuit (IC) device comprises a high voltage semiconductor device (HVSD) on a frontside of a semiconductor body and further comprises an electrode on a backside of the semiconductor body opposite the frontside. The HVSD may for example, be a transistor or some other suitable type of semiconductor device. The electrode has one or more gaps directly beneath the HVSD. The one or more gaps enhance the effectiveness of the electrode for improving the breakdown voltage of the HVSD.

Abstract: A touch panel includes a substrate, a plurality of control signal lines, a plurality of first reading signal lines, and a plurality of second reading signal lines. The plurality of control signal lines are disposed on a first surface of the substrate and spaced from each other. The plurality of first reading signal lines are disposed on a second surface of the substrate and spaced from each other. The second surface is opposite to the first surface. The plurality of second reading signal lines are disposed on the first surface of the substrate. Each of the plurality of second reading signal lines is located between adjacent two of the plurality of control signal lines. An electronic device including the above touch panel is also provided.

Abstract: An electronic device includes a display panel having a display surface and a touch panel located above the display surface. The touch panel includes a substrate, first electrode series, and second electrode series. The first electrode series are disposed on the substrate and each include first electrode portions and connection portions each connecting adjacent two first electrode portions in series in a first direction. The second electrode series are disposed on the substrate and each include second electrode portions and second connection portions each connecting adjacent two second electrode portions in series in a second direction intersecting the first direction. Each first connection portion partially overlaps one second connection portion. The first electrode portions and the second electrode portions are disposed in parallel on the substrate. An area of each second electrode portion is larger than an area of each first electrode portion.

Abstract: A capacitor structure comprises a substrate having a first side, a second side opposite to the first side and an upper surface corresponding to the first side; a plurality of first trenches formed on the first side of the substrate, disposed along a first direction and a second direction parallel to the upper surface, and penetrating the substrate along a third direction, the first direction, the second direction and the third direction orthogonal to each other; a plurality of second trenches formed on the second side of the substrate and penetrating the substrate along the third direction, the first trenches and the second trenches separated from each other in the first direction; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches.

Abstract: A method for manufacturing a capacitor structure is provided. A substrate having a first side and a second side opposite to the first side is provided. A plurality of first trenches are formed on the first side. A first capacitor is formed extending along the first side and into the first trenches. A plurality of second trenches are formed on the second side. A second capacitor is formed extending along the second side and into the second trenches.

Abstract: A switching power converter for converting an input power to an output power includes a power stage; and a conversion control circuit which includes: a current limit control circuit for comparing a current monitor signal and a sensing signal limit threshold to generate a current limit control signal, wherein the current monitor signal is related to an output current of the output power; and a PWM control circuit for generating a PWM signal according to an output voltage of the output power for controlling the power stage to generate the output power. The first state of the PWM signal has a first constant time. When the current limit control signal indicates that the output current exceeds a current limit threshold, the PWM control circuit controls a switching frequency of the PWM signal to operate at a fixed frequency. The fixed frequency is lower than a predetermined frequency limit.

Abstract: A device performs a method for using image data to aid voice recognition. The method includes the device capturing image data of a vicinity of the device and adjusting, based on the image data, a set of parameters for voice recognition performed by the device. The set of parameters for the device performing voice recognition include, but are not limited to: a trigger threshold of a trigger for voice recognition; a set of beamforming parameters; a database for voice recognition; and/or an algorithm for voice recognition. The algorithm may include using noise suppression or using acoustic beamforming.