Abstract: A circuit structure includes a substrate, a III-V semiconductor compound over the substrate, a AlxGa(1?x)N (AlGaN) layer over the III-V semiconductor compound, a gate over the AlGaN layer, a passivation film over the gate and over a portion of the AlGaN layer, a source structure, and a drain structure on an opposite side of the gate from the source structure, wherein X ranges from 0.1 to 1. The source structure has a source contact portion and an overhead portion. The overhead portion is over at least a portion of the passivation film between the source contact portion and the gate. A distance between the source contact portion and the gate is less than a distance between the gate and the drain structure.

Abstract: A method of forming a high electron mobility transistor (HEMT) includes epitaxially growing a second III-V compound layer on a first III-V compound layer. The method further includes partially etching the second III-V compound layer to form two through holes in the second III-V compound layer. Additionally, the method includes forming a silicon feature in each of two through holes. Furthermore, the method includes depositing a metal layer on each silicon feature. Moreover, the method includes annealing the metal layer and each silicon feature to form corresponding salicide source/drain features. The method also includes forming a gate electrode over the second III-V compound layer between the salicide source/drain features.

Abstract: An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.

Abstract: A method of forming a semiconductor structure includes forming a second III-V compound layer over a first III-V compound layer, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer. The method further includes forming a source feature and a drain feature over the second III-V compound layer. The method further includes forming a gate dielectric layer over the second III-V compound layer, wherein the gate dielectric layer is over a top surface of the source feature and over a top surface of the drain feature. The method further includes treating a portion of the gate dielectric layer with fluorine, wherein treating the portion of the gate dielectric layer comprises performing an implantation process using at least one fluorine-containing compound. The method further includes forming a gate electrode over the portion of the gate dielectric layer.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. A first III-V compound layer is disposed over the silicon substrate. A second III-V compound layer is disposed over the first III-V compound layer. The semiconductor device includes a transistor disposed over the first III-V compound layer and partially in the second III-V compound layer. The semiconductor device includes a diode disposed in the silicon substrate. The semiconductor device includes a via coupled to the diode and extending through at least the first III-V compound layer. The via is electrically coupled to the transistor or disposed adjacent to the transistor.

Abstract: A method comprises epitaxially growing a gallium nitride (GaN) layer over a silicon substrate, epitaxially growing a donor-supply layer over the GaN layer, and etching a portion of the donor-supply layer. The method also comprises depositing a passivation layer over the donor-supply layer and filling the etched portion of the donor-supply layer, forming a source and a drain on the donor-supply layer, and forming a gate structure between the source and the etched portion of the donor-supply layer. The method further comprises depositing contacts over the gate structure, the source, and the drain.

Abstract: An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.

Abstract: A method of making a high-electron mobility transistor (HEMT) includes forming an unintentionally doped gallium nitride (UID GaN) layer over a silicon substrate, a donor-supply layer over the UID GaN layer, a gate, a passivation layer over the gate and portions of the donor-supply layer, an ohmic source structure and an ohmic drain structure over the donor-supply layer and portions of the passivation layer. The source structure includes a source contact portion and an overhead portion. The overhead portion overlaps the passivation layer between the source contact portion and the gate, and may overlap a portion of the gate and a portion of the passivation layer between the gate and the drain structure.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

Abstract: A method of forming a high electron mobility transistor (HEMT) includes forming a second III-V compound layer on a first III-V compound layer, forming a source feature and a drain feature on the second III-V compound layer, depositing a p-type layer on a portion of the second III-V compound layer between the source feature and the drain feature, and forming a gate electrode on the p-type layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer.

Abstract: A semiconductor structure comprises a first layer. The first layer comprises a first III-V semiconductor material. The semiconductor structure also comprises a second layer over the first layer. The second layer comprises a second III-V semiconductor material different from the first III-V semiconductor material. The semiconductor structure further comprises an insulating layer over the second layer. The insulating layer is patterned to expose a portion of the first layer. The exposed portion of the first layer comprises electrons of the second layer. The semiconductor structure additionally comprises an intermetallic compound over the exposed portion of the first layer.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A carrier channel depleting layer is disposed on the second III-V compound layer. The carrier channel depleting layer is deposited using plasma and a portion of the carrier channel depleting layer is under at least a portion of the gate electrode.

Abstract: A method of making a circuit structure includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain.

Abstract: A method includes epitaxially growing a gallium nitride (GaN) layer over a silicon substrate. The method further includes epitaxially growing a donor-supply layer over the GaN layer. The method further includes forming a source and a drain on the donor-supply layer. The method further includes forming a gate structure between the source and the drain on the donor-supply layer. The method further includes plasma etching a portion of a drift region of the donor-supply layer to a depth of less than 60% of a donor-supply layer thickness. The method further includes depositing a dielectric layer over the donor-supply layer.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. Each of the source feature and the drain feature comprises a corresponding intermetallic compound at least partially embedded in the second III-V compound layer. Each intermetallic compound is free of Au and comprises Al, Ti or Cu. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A depletion region is disposed in the carrier channel and under the gate electrode.

Abstract: The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device.

Abstract: A method of forming a semiconductor structure having a substrate is disclosed. The semiconductor structure includes a first layer formed in contact with the substrate. The first layer made of a first III-V semiconductor material selected from GaN, GaAs and InP. A second layer is formed on the first layer. The second layer made of a second III-V semiconductor material selected from AlGaN, AlGaAs and AlInP. An interface is between the first layer and the second layer forms a carrier channel. An insulating layer is formed on the second layer. Portions of the insulating layer and the second layer are removed to expose a top surface of the first layer. A metal feature is formed in contact with the carrier channel and the metal feature is annealed to form a corresponding intermetallic compound.

Abstract: A transistor includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a metal diffusion barrier over the active layer, and a gate over the metal diffusion barrier. The active layer has a band gap discontinuity with the channel layer.

Abstract: A circuit structure includes a substrate, an unintentionally doped gallium nitride (UID GaN) layer over the substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. A number of islands are over the donor-supply layer between the gate structure and the drain. The gate structure disposed between the drain and the source. The gate structure is adjoins at least a portion of one of the islands and/or partially disposed over at least a portion of at least one of the islands.