Abstract: A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.

Abstract: The present invention introduces a new shielded gate trench MOSFETs wherein epitaxial layer having special multiple stepped epitaxial (MSE) layers with different doping concentrations decreasing in a direction from substrate to body regions, wherein each of the MSE layers has uniform doping concentration as grown. Specific on-resistance is significantly reduced with the special MSE structure. Moreover, in sore preferred embodiment, an MSO (multiple stepped oxide) structure is applied to the shielded gate structure to further reduce the specific on-resistance and enhance device ruggedness.

Abstract: A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped shielded electrode in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability.

Abstract: An improved SiC trench MOSFET having first and second type gate trenches for formation of a gate electrode, and a grounded P-shield region under the gate electrode for gate oxide electric-field reduction is disclosed. The gate electrodes are disposed into the first type gate trench having a thick oxide layer on trench bottom. The grounded P-shield region surrounding the second type gate trench filled up with the thick oxide layer is connected with a source metal through a grounded P region. The device further comprises a current spreading region surrounding the first type gate trench for on-resistance reduction.

Abstract: A SiC SJ trench MOSFET having first and second type gate trenches for formation of gate electrodes and super junction regions is disclosed. The gate electrodes are disposed into the first type gate trenches having a thick oxide layer on trench bottom. The super junction regions are formed surrounding the second type gate trenches filled up with the thick oxide layer. The device further comprises gate oxide electric field reducing regions adjoining lower surfaces of body regions and space apart from the gate trenches.

Abstract: A SiC SJ trench MOSFET having first and second type gate trenches for formation of gate electrodes and super junction regions is disclosed. The gate electrodes are disposed into the first type gate trenches having a thick oxide layer on trench bottom. The super junction regions are formed surrounding the second type gate trenches filled up with the thick oxide layer. The device further comprises gate oxide electric field reducing regions adjoining lower surfaces of body regions and space apart from the gate trenches.

Abstract: An improved SGT MOSFET having low on-resistance is disclosed in this invention by adding a current spreading region under body region and a method to manufacture the same. With a doping concentration higher than the drift region, the inventive current spreading region can help reducing on-resistance while remaining a target breakdown voltage. Meanwhile, the present invention also features a method of formation of a new MSO structure with LOCOS technique for further improving on-resistance.

Abstract: A SGT MOSFET having two stepped oxide (TSO) structure in gate trench is disclosed, wherein the TSO has thinner oxide thickness along upper sidewalls of the gate trench than along lower sidewalls of the gate trench. The BV can be enhanced as result of the electric filed reduction near channel region, on-resistance is thus reduced. The present invention further comprises a super junction region below the oxide charge balance region, making vertical electrical field more uniform, the BV is further enhanced and on-resistance is further reduced.

Abstract: A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.

Abstract: An integrated circuit comprising an SGT MOSFET and a short channel SBR is disclosed. The SBR horizontally disposed in different areas to the SGT MOSFET on single chip creates a low potential barrier for majority carrier in MOS channel for switching loss reduction. Only one additional mask is required for integration of the short channel SBR having thinner gate oxide than the SGT MOSFET. Moreover, in some preferred embodiment, an MSO structure is applied to the shielded gate structure to further reduce the on-resistance.

Abstract: A SGT MOSFET having two stepped oxide (TSO) structure in gate trench is disclosed, wherein the TSO has thinner oxide thickness along upper sidewalls of the gate trench than along lower sidewalls of the gate trench. The BV can be enhanced as result of the electric filed reduction near channel region, on-resistance is thus reduced. The present invention further comprises a super junction region below the oxide charge balance region, making vertical electrical field more uniform, the BV is further enhanced and on-resistance is further reduced.

Abstract: A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.

Abstract: A SiC SJ trench MOSFET having first and second type gate trenches for formation of gate electrodes and super junction regions is disclosed. The gate electrodes are disposed into the first type gate trenches having a thick oxide layer on trench bottom. The super junction regions are formed surrounding the second type gate trenches filled up with the thick oxide layer. The device further comprises gate oxide electric field reducing regions adjoining lower surfaces of body regions and space apart from the gate trenches.

Abstract: The present invention discloses an embedding structure for a wheel cover fitted to an aluminum alloy wheel rim. It comprises a wheel cover having a long slot at a middle, plural engaging legs around the long slot at an inner end surface and each having a positioning protrusion at an outer terminal toward the long slot, two withstanding protrusions protruded from an outer end surface at two ends of the long slot and an engaging groove between the two withstanding protrusions; and a supporting seat disposed in a space defined by the plural engaging legs which has a connection segment at a middle, a tenon connected to the connection segment and corresponding to the long slot, an annular groove formed at an outer edge and corresponding to the positioning protrusion of each of the plural engaging legs for pushing the positioning protrusions outwardly and expanding the plural engaging legs outwardly.

Abstract: A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped gate shielded electrodes in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability.

Abstract: An SGT MOSFET having super junction surrounding lower portion of trenched gates is disclosed. The super junction structure is surrounding lower portion of trenched gates to ensure whole drift region is fully depleted and breakdown occurs at middle of adjacent trenched gates without having early breakdown occurring at trench bottom. Moreover, sensitivity of breakdown voltage on trench bottom oxide thickness and trench depth is significantly relaxed or immune. Avalanche capability is also enhanced.

Abstract: An integrated circuit comprising an SGT MOSFET and a short channel SBR is disclosed. The SBR horizontally disposed in different areas to the SGT MOSFET on single chip creates a low potential barrier for majority carrier in MOS channel for switching loss reduction. Only one additional mask is required for integration of the short channel SBR having thinner gate oxide than the SGT MOSFET. Moreover, in some preferred embodiment, an MSO structure is applied to the shielded gate structure to further reduce the on-resistance.

Abstract: A trenched semiconductor power device is disclosed comprising a plurality of trenched gates, each including a pair of split gate electrodes and a shielded gate electrode forming an oxide charge balance region between adjacent trenched gates, and junction charge balance region below trench bottom. The trenched semiconductor power device further comprises a super junction structure including a plurality of alternating P and N regions disposed above a substrate forming a junction charge balance region below the oxide charge balance region for breakdown voltage enhancement and on-resistance reductions.

Abstract: A trenched semiconductor power device is disclosed comprising a plurality of trenched gates, each including a gate electrode and a shielded gate electrode forming an oxide charge balance region between adjacent trenched gates; and the trenched semiconductor power device further comprises a super junction structure including a plurality of alternating P and N regions disposed above a substrate and forming a junction charge balance region below the oxide charge balance region for breakdown voltage enhancement, on-resistance and output capacitance reductions.

Abstract: An integrated circuit comprising a surrounding gate transistor (SGT) MOSFET and a super barrier rectifier (SBR) is disclosed. The SBR horizontally disposed in different areas to the SGT MOSFET on single chip creates a low potential barrier for majority carrier in MOS channel, therefore has lower forward voltage and reverse leakage current than conventional Schottky Barrier Rectifier. Moreover, in some preferred embodiment, a multiple stepped oxide (MSO) structure is applied to the shielded gate structure to further reduce the on-resistance.