Abstract: A SiC trench MOSFET with an embedded junction Schottky barrier diode (JBSD) having P-shield (PS) regions surrounding bottoms of source-body-Schottky contact (SBSC) trenches for gate oxide electric-field and switching loss reductions is disclosed. A source metal connects with the PS regions and the JBSD directly. Sidewall P (SP) regions are formed along a portion of sidewalls of the SBSC trenches to improve a tradeoff between a drain-source leakage current of the SiC trench MOSFET and a forward voltage of the JBSD. The device further comprises an N-type shield region formed below each of gate trenches for gate oxide electric field strength and specific on-resistance reductions.

Abstract: Shielded gate trench MOSFETs with gate trenches separated from termination trenches are disclosed, wherein at least one termination trench surrounds outer periphery of gate trenches and does not surround the gate metal pad area. The shielded gate electrode inside each of the gate trenches is connected to a source metal through at least one shielded gate trench contact which is spaced apart from at least one gate metal runner with a distance larger than 100 um. A breakdown voltage enhancement region and an avalanche capability enhancement region in the device structures are also disclosed.

Abstract: The present invention introduces a new shielded gate trench MOSFETs with improved specific on-resistance and avalanche capability structures including an active area and an edge termination area, wherein an epitaxial layer having special multiple stepped epitaxial (MSE) layers in an oxide charge balance (OCB) region, and an edge termination having multiple trench field plates, and electric field reducing regions disposed surrounding bottom of gate trenches with a doping concentration lower than said bottom epitaxial layer of the MSE layers. Moreover, in some preferred embodiment, a multiple stepped oxide structure in the OCB region, and an epitaxial layer in a buffer region below the OCB region with a doping concentration lower than the MSE layers is introduced to further reduce the specific on-resistance and enhance device ruggedness.

Abstract: An improved SiC trench MOSFET having N-type and P-type shield zones for gate oxide electric-field reduction is disclosed. The N-type shield zones are formed below a gate electrode and the P-type shield zones adjoin lower surfaces of the body regions. The device further comprises a current spreading region surrounding at least sidewalls of the gate trenches for on-resistance reduction.

Abstract: Shielded gate trench MOSFETs with gate trenches separated from termination trenches are disclosed, wherein the termination trenches surrounds outer periphery of gate trenches and do not surround said gate metal pad area; Inner edges of a first termination trench of the termination trenches adjacent to trench ends of the gate trenches have a plurality of wave shape portions in regions between two adjacent trench ends of the gate trenches while outer edges have a straight shape to reduce drain-source leakage current. Each of gate trenches on which has at least one shielded gate trench contact connected to a shielded gate electrode, and the shielded gate trench contact is spaced apart from any of multiple gate metal runners with a distance larger than 100 um.

Abstract: The present invention introduces a new shielded gate trench SBR (Super Barrier Rectifier) wherein an epitaxial layer having special MSE (multiple stepped epitaxial) layers with different doping concentrations decreasing in a direction from a substrate to a top surface of the epitaxial layer, wherein each of the MSE layers has an uniform doping concentration as grown. Forward voltage Vf is significantly reduced with the special MSE layers. An integrated circuit comprising a SGT MOSFET and a SBR formed on a single chip obtains benefits of low on-resistance, low reverse recovery time and high avalanche capability from the special MSE layers.

Abstract: Shielded gate devices having a planarized thermally grown (PTG) inter-poly oxide (IPO) structure are disclosed. By using a method having double wet etching processes of a field oxide and double dry etching processes of a first doped polysilicon, the PTG IPO structure is achieved to reduce gate-source leakage current Igss and gate resistance Rg. A gate oxide and a PTG IPO are thermally grown simultaneously. The devices further comprise a current spreading region surrounding a lower portion of a gate electrode for on-resistance reduction.

Abstract: A SiC shielded gate trench device having a first type gate trench and a second type gate trench is disclosed. The first type gate trench is above the second type gate trench and has a trench width wider than a trench width of the second type gate trench, wherein the first type gate trench is filled with a gate electrode and a shielded gate electrode, and a grounded P-shield region surrounding the second type gate trench is under the shielded gate electrode for gate oxide electric-field reduction. The device further comprises a current spreading region surrounding the gate electrode for on-resistance reduction.

Abstract: A SGT MOSFET and a SGT super barrier rectifier having improved on-resistance and gate charge structures are disclosed in this invention by applying a short channel implant region for formation of a shorter channel length after body implantation and diffusion, and by introducing a super junction region below an oxide charge balance region for breakdown voltage enhancement. The present invention can further achieve a lower specific on-resistance by applying multiple stepped epitaxial layers or multiple stepped oxide structure.

Abstract: A shielded gate trench (SGT) MOSFET structure with a hexagonal deep trench layout and multiple epitaxial layers for wafer warpage and on-resistance reductions is disclosed, wherein a gate electrode surrounds the deep trench in each unit cell as a closed cell. A source-body contact is disposed between the gate electrode and the deep trench. Moreover, the gate electrode is planar, or vertically formed in an upper portion of a gate trench in each unit cell.

Abstract: A shielded gate trench (SGT) MOSFET with a square or rectangular pillar-shape deep trench and multiple epitaxial layers is disclosed, wherein at least one gate electrode surrounds the deep trench in each wait cell. The at least one gate electrode is planar, or vertically formed in an upper portion of a gate trench in each wait cell. Moreover, a body region is absent in an intersection area of two gate trenches adjacent to corners of the deep trench for breakdown voltage enhancement.

Abstract: Shielded gate trench MOSFETs with gate trenches separated from termination trenches are disclosed, wherein a first type body regions are formed in an active area and an first type electric field reducing regions formed adjacent to an intersection regions between a first termination trench and trench ends of gate trenches; The first type electric field reducing regions formed between the first type body regions and the first termination trench wherein the first type body regions are absent to enhance breakdown voltage. At least one second type body region of the second conductivity type with a floating voltage is formed within the first type field reducing regions, and is spaced apart from the first type body regions and the first termination trench for further increasing breakdown voltage.

Abstract: The present invention introduces new shielded gate trench (SGT) superjunction (SJ) MOSFETs having a first type multiple stepped epitaxial (MSE) structure in oxide charge balance (OCB) region and a second type MSE structure in SJ region for improved specific on-resistance Rsp and gate-to-drain charge Qgd. The two-type MSE structures can increase the average doping concentration in drift regions of the SGT SJ MOSFETS, as a result, lower Rsp and higher avalanche capability could be achieved without degrading breakdown voltage.

Abstract: Shielded gate trench MOSFETs with gate trenches separated from termination trenches are disclosed, wherein the termination trenches surrounds outer periphery of gate trenches and do not surround said gate metal pad area; Inner edges of a first termination trench of the termination trenches adjacent to trench ends of the gate trenches have a plurality of wave shape portions in regions between two adjacent trench ends of the gate trenches while outer edges have a straight shape to reduce drain-source leakage current. Each of gate trenches on which has at least one shielded gate trench contact connected to a shielded gate electrode, and the shielded gate trench contact is spaced apart from any of multiple gate metal runners with a distance larger than 100 um.

Abstract: Shielded gate trench MOSFETs with gate trenches separated from termination trenches are disclosed, wherein at least one termination trench surrounds outer periphery of gate trenches and does not surround the gate metal pad area. The shielded gate electrode inside each of the gate trenches is connected to a source metal through at least one shielded gate trench contact which is spaced apart from at least one gate metal runner with a distance larger than 100 um. A breakdown voltage enhancement region and an avalanche capability enhancement region in the device structures are also disclosed.

Abstract: The present invention introduces a new shielded gate trench MOSFETs with improved specific on-resistance and avalanche capability structures including an active area and an edge termination area, wherein an epitaxial layer having special multiple stepped epitaxial (MSE) layers in an oxide charge balance (OCB) region, and an edge termination having multiple trench field plates, and electric field reducing regions disposed surrounding bottom of gate trenches with a doping concentration lower than said bottom epitaxial layer of the MSE layers. Moreover, in some preferred embodiment, a multiple stepped oxide structure in the OCB region, and an epitaxial layer in a buffer region below the OCB region with a doping concentration lower than the MSE layers is introduced to further reduce the specific on-resistance and enhance device ruggedness.

Abstract: An improved SiC trench MOSFET having first and second type gate trenches for formation of a gate electrode, and a grounded P-shield region under the gate electrode for gate oxide electric-field reduction is disclosed. The gate electrodes are disposed into the first type gate trench having a thick oxide layer on trench bottom. The grounded P-shield region surrounding the second type gate trench filled up with the thick oxide layer is connected with a source metal through a grounded P region. The device further comprises a current spreading region surrounding the first type gate trench for on-resistance reduction.

Abstract: The present invention introduces a new shielded gate trench SBR (Super Barrier Rectifier) wherein an epitaxial layer having special MSE (multiple stepped epitaxial) layers with different doping concentrations decreasing in a direction from a substrate to a top surface of the epitaxial layer, wherein each of the MSE layers has an uniform doping concentration as grown. Forward voltage Vf is significantly reduced with the special MSE layers. An integrated circuit comprising a SGT MOSFET and a SBR formed on a single chip obtains benefits of low on-resistance, low reverse recovery time and high avalanche capability from the special MSE layers.

Abstract: A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.

Abstract: The present invention introduces a new shielded gate trench MOSFETs wherein epitaxial layer having special multiple stepped epitaxial (MSE) layers with different doping concentrations decreasing in a direction from substrate to body regions, wherein each of the MSE layers has uniform doping concentration as grown. Specific on-resistance is significantly reduced with the special MSE structure. Moreover, in sore preferred embodiment, an MSO (multiple stepped oxide) structure is applied to the shielded gate structure to further reduce the specific on-resistance and enhance device ruggedness.