Patents by Inventor Fu-Yuan Hsieh

Fu-Yuan Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated trench MOSFET with trench Schottky rectifier
    Patent number: 8722434
    Abstract: An integrated circuit comprising trench MOSFET having trenched source-body contacts and trench Schottky rectifier having trenched anode contacts is disclosed. By employing the trenched contacts in trench MOSFET and trench Schottky rectifier, the integrated circuit is able to be shrunk to achieve low specific on-resistance for trench MOSFET, and low Vf and reverse leakage current for trench Schottky Rectifier.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: May 13, 2014
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Trench metal oxide semiconductor field effect transistor with embedded schottky rectifier using reduced masks process
    Patent number: 8723317
    Abstract: A trench MOSFET with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 13, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • TRENCH MOSFET HAVING A TOP SIDE DRAIN
    Publication number: 20140120672
    Abstract: This invention discloses a trench MOSFET comprising a top side drain region in a wide trench in a termination area besides a BV sustaining area, wherein said top side drain comprises a top drain metal connected to an epitaxial layer and a substrate through a plurality of trenched drain contacts, wherein the wide trench is formed simultaneously when a plurality of gate trenches are formed in an active area, and the trenched drain contacts are formed simultaneously when a trenched source-body contact is formed in the active area.
    Type: Application
    Filed: January 7, 2014
    Publication date: May 1, 2014
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan HSIEH
  • Trench metal oxide semiconductor field effect transistor with multiple trenched source-body contacts for reducing gate charge
    Patent number: 8704297
    Abstract: A trench MOSFET with multiple trenched source-body contacts is disclosed for reducing gate charge by applying multiple trenched source-body contacts in unit cell. Furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: April 22, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH MULTIPLE TRENCHED SOURCE-BODY CONTACTS FOR REDUCING GATE CHARGE
    Publication number: 20140103426
    Abstract: A trench MOSFET with multiple trenched source-body contacts is disclosed for reducing gate charge by applying multiple trenched source-body contacts in unit cell. Furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Inventor: FU-YUAN HSIEH
  • Semiconductor power device having wide termination trench and self-aligned source regions for mask saving
    Patent number: 8686468
    Abstract: A trench semiconductor power device with a termination area structure is disclosed. The termination area structure comprises a wide trench and a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide trench by doing poly-silicon CMP so that the body ion implantation is blocked by the trenched field plate on the trench bottom to prevent the termination area underneath the wide trench from being implanted. Moreover, a contact mask is used to define both trenched contacts and source regions of the device for saving a source mask.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: April 1, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Trench MOSFET having floating dummy cells for avalanche improvement
    Patent number: 8680610
    Abstract: A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: March 25, 2014
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH EMBEDDED SCHOTTKY RECTIFIER USING REDUCED MASKS PROCESS
    Publication number: 20140077290
    Abstract: A trench MOSFET with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventor: FU-YUAN HSIEH
  • Semiconductor power device integrated with ESD protection diodes
    Patent number: 8658492
    Abstract: A semiconductor power device integrated with ESD protection diode is disclosed by offering a dopant out-diffusion suppression layers prior to source dopant activation or diffusion to enhance ESD protection capability between gate and source.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: February 25, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • AVALANCHE CAPABILITY IMPROVEMENT IN POWER SEMICONDUCTOR DEVICES USING THREE MASKS PROCESS
    Publication number: 20140048872
    Abstract: A power semiconductor device with improved avalanche capability is disclosed by forming at least one avalanche capability enhancement doped region underneath an ohmic contact doped region. Moreover, a source mask is saved by using three masks process and the avalanche capability is further improved.
    Type: Application
    Filed: July 24, 2013
    Publication date: February 20, 2014
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: FU-YUAN HSIEH
  • Trench MOSFET with ultra high cell density and manufacture thereof
    Patent number: 8652900
    Abstract: A trench MOSFET structure with ultra high cell density is disclosed, wherein the source regions and the body regions are located in different regions to save the mesa area between every two adjacent gate trenches in the active area. Furthermore, the inventive trench MOSFET is composed of stripe cells to further increase cell packing density and decrease on resistance Rds between the drain region and the source region.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: February 18, 2014
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Trench MOSFET having a top side drain
    Patent number: 8653587
    Abstract: This invention discloses a trench MOSFET comprising a top side drain region in a wide trench in a termination area besides a BV sustaining area, wherein said top side drain comprises a top drain metal connected to an epitaxial layer and a substrate through a plurality of trenched drain contacts, wherein the wide trench is formed simultaneously when a plurality of gate trenches are formed in an active area, and the trenched drain contacts are formed simultaneously when a trenched source-body contact is formed in the active area.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: February 18, 2014
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Low Qgd trench MOSFET integrated with schottky rectifier
    Patent number: 8653589
    Abstract: An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trenched gates sidewalls for reducing Qgd; a source dopant region disposed below trench bottoms of all trenched gates for functioning as a current path for preventing a resistance increased caused by the tilt-angle implanted body dopant regions.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: February 18, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Super-junction trench MOSFET with multiple trenched source-body contacts
    Patent number: 8648413
    Abstract: A super-junction trench MOSFET with split gate electrodes is disclosed for high voltage device by applying multiple trenched source-body contacts with narrow CDs in unit cell. Furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: February 11, 2014
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Shielded trench MOSFET with multiple trenched floating gates as termination
    Patent number: 8643092
    Abstract: A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: February 4, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Semiconductor power device having improved termination structure for mask saving
    Patent number: 8614482
    Abstract: A improved termination structure for semiconductor power devices is disclosed, comprising a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide termination trench by doing poly-silicon CMP so that body ion implantation is blocked by the trenched field plate on the trench bottom to prevent a body region formation underneath the trench bottom of the wide termination trench, degrading avalanche voltage.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: December 24, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • TRENCH MOSFET WITH TRENCHED FLOATING GATES HAVING THICK TRENCH BOTTOM OXIDE AS TERMINATION
    Publication number: 20130330892
    Abstract: A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask.
    Type: Application
    Filed: July 29, 2013
    Publication date: December 12, 2013
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • Fast switching hybrid IGBT device with trenched contacts
    Patent number: 8598624
    Abstract: A hybrid IGBT device having a VIGBT and LDMOS structures comprises at least a drain trenched contact filled with a conductive plug penetrating through an epitaxial layer, and extending into a substrate; a vertical drain region surrounding at least sidewalls of the drain trenched contact, extending from top surface of the epitaxial layer to the substrate, wherein the vertical drain region having a higher doping concentration than the epitaxial layer.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: December 3, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • TRENCH MOSFET WITH TRENCHED FLOATING GATES HAVING THICK TRENCH BOTTOM OXIDE AS TERMINATION
    Publication number: 20130307066
    Abstract: A semiconductor power device with trenched floating gates having thick bottom oxide as termination is disclosed. The gate charge is reduced by forming a HDP oxide layer padded by a thermal oxide layer on trench bottom and a top surface of mesa areas between adjacent trenched gates. Therefore, only three masks are needed to achieve the device structure.
    Type: Application
    Filed: July 29, 2013
    Publication date: November 21, 2013
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: FU-YUAN HSIEH
  • Trench MOSFET with resurf stepped oxide and diffused drift region
    Patent number: 8587054
    Abstract: A trench MOSFET with split gates and diffused drift region for on-resistance reduction is disclosed. Each of the split gates is symmetrically disposed in the middle of the source electrode and adjacent trench sidewall of a deep trench. The inventive structure can save a mask for definition of the location of the split gate electrodes. Furthermore, the fabrication method can be implemented more reliably with lower cost.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: November 19, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh