Patents by Inventor Fu-Yuan Hsieh

Fu-Yuan Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180072094
    Abstract: A wheel cover of an aluminum alloy wheel is revealed. The wheel cover is located on and covered an outer side of the aluminum alloy wheel. A peripheral wall is axially extended from a circumference of a central insertion hole of the wheel cover. The peripheral wall is fitted into a central insertion hole of the aluminum alloy wheel. A locking part on each spring arranged around the peripheral wall is locked with an inner edge of the insertion hole of the aluminum alloy wheel. The production of the aluminum alloy wheel is generally based on the central insertion hole thereof. The wheel cover and the insertion hole are connected mainly at the central insertion hole owing to precision of the size and position of the central insertion hole. Thereby the wheel cover and the aluminum alloy wheel are assembled conveniently.
    Type: Application
    Filed: September 12, 2016
    Publication date: March 15, 2018
    Inventor: FU-YUAN HSIEH
  • Publication number: 20170317207
    Abstract: A trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 2, 2017
    Inventor: Fu-Yuan HSIEH
  • Publication number: 20170278837
    Abstract: A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed, wherein: the shielded gate structure comprises a first poly-silicon layer to serve as a shielded electrode and a second poly-silicon layer to serve as a gate electrode, and the ESD clamp diode formed between two protruding electrodes is also formed by the first poly-silicon layer. A mask specially used to define the ESD clamp diode portion is saved.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 28, 2017
    Inventor: Fu-Yuan HSIEH
  • Patent number: 9530867
    Abstract: A method for manufacturing a super junction trench MOSFET by growing a first epitaxial layer of a first conductivity type upon a heavily doped substrate layer of a first conductivity type; forming a deep trench mask covering a top surface of the first epitaxial layer; applying a trench mask to form a deep trench extending into the substrate layer by successively dry oxide etch and dry silicon etch; and carrying out angle ion implantations of the first conductivity type dopant and driving-in to form a first type column regions with column shape within the first epitaxial layer; and carrying out angle ion implantations of a second conductivity type dopant and diffusion to form a second type column regions with column shape adjacent to sidewalls of the deep trench, in parallel with and surrounding the first type column regions; and removing the hard mask.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: December 27, 2016
    Assignee: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 9530882
    Abstract: A trench MOSFET with diffused drift region and closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: December 27, 2016
    Assignee: FORCE MOS TECHNOLOGY CO., LTD
    Inventor: Fu-Yuan Hsieh
  • Patent number: 9412810
    Abstract: A super-junction trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are at least formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: August 9, 2016
    Assignee: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20160163789
    Abstract: A super-junction trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are at least formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.
    Type: Application
    Filed: January 8, 2015
    Publication date: June 9, 2016
    Inventor: Fu-Yuan HSIEH
  • Patent number: 9337328
    Abstract: A super-junction trench MOSFET with closed cell layout is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell. Trenched source-body contacts are disposed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: May 10, 2016
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20160104702
    Abstract: A super-junction trench MOSFET integrated with embedded trench Schottky rectifier is disclosed for soft reverse recovery operation. The embedded trench Schottky rectifier can be integrated in a same unit cell with the super-junction trench MOSFET.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 14, 2016
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: FU-YUAN HSIEH
  • Patent number: 9293527
    Abstract: A super-junction trench MOSFET is disclosed by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches with buried voids in each unit cell for super-junction. A buffer poly-silicon layer is deposited above the buried void for stress release to prevent wafer crack and silicon defects.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 22, 2016
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20150318379
    Abstract: A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier.
    Type: Application
    Filed: July 15, 2015
    Publication date: November 5, 2015
    Inventor: FU-YUAN HSIEH
  • Publication number: 20150221733
    Abstract: A trench MOSFET structure having self-aligned features for mask saving and on-resistance reduction is disclosed, wherein source regions are formed by performing source Ion Implantation through contact holes of a contact interlayer in the middle of adjacent terrace trenched gates, and further source diffusion. Both the contact holes and source regions are self-aligned to the terrace trenched gates.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: FU-YUAN HSIEH
  • Patent number: 9099320
    Abstract: A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: August 4, 2015
    Assignee: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 9018701
    Abstract: A power semiconductor device with improved avalanche capability is disclosed by forming at least one avalanche capability enhancement doped region underneath an ohmic contact doped region. Moreover, a source mask is saved by using three masks process and the avalanche capability is further improved.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: April 28, 2015
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 9000515
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: April 7, 2015
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8999789
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 7, 2015
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20150076594
    Abstract: A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: FU-YUAN HSIEH
  • Publication number: 20150037954
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventor: FU-YUAN HSIEH
  • Patent number: 8907415
    Abstract: A shielded gate trench metal oxide semiconductor filed effect transistor (MOSFET) having high switching speed is disclosed. The inventive shielded gate trench MOSFET includes a shielded electrode spreading resistance placed between a shielded gate electrode and a source metal to enhance the performance of the shielded gate trench MOSFET by adjusting doping concentration of poly-silicon in gate trenches to a target value. Furthermore, high cell density is achieved by employing the inventive shielded gate trench MOSFET without requirement of additional cost.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: December 9, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20140346593
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: FU-YUAN HSIEH