Abstract: A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped shielded electrode in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability.

Abstract: A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped shielded electrode in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability.

Abstract: A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of multiple trench MOSFETs connected together with multiple sawing trenched gates across a space between two trench MOSFETs having a width same as scribe line. Dummy cells formed between an edge trench and active area act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.

Abstract: A shielded gate trench MOSFET with multiple stepped oxide (MSO) structure surrounding the shielded gate in termination area is disclosed. The inventive structure can reduce specific on-resistance and support enough breakdown voltage, simultaneously. The device structure termination is achieved using angle implant of N and P columns.

Abstract: An integrated circuit comprising a SGT MOSFET and a SBR is disclosed. The SBR horizontally disposed in different areas to the SGT MOSFET on single chip creates a low potential barrier for majority carrier in MOS channel, therefore has lower forward voltage and reverse leakage current than conventional Schottky Barrier Rectifier. Moreover, in some preferred embodiment, a MSO structure is applied to the shielded gate structure to further reduce the on-resistance.

Abstract: A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of multiple trench MOSFETs connected together with multiple sawing trenched gates across a space between two trench MOSFETs having a width same as scribe line. Dummy cells formed between an edge trench and active area act as butler cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.

Abstract: A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped shielded electrode in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching.

Abstract: A trench MOSFET is disclosed having shielded trenched gates in active area, multiple floating trenched gates and at least one channel stop trenched gate in termination area. A semiconductor power device layout is disclosed consisting of at least two said trench MOSFETs connected together with multiple sawing trenched gates across a space between the two trench MOSFETs having a width same as scribe line, making the invented trench MOSFET be feasibly achieved without degraded performance.

Abstract: A trench MOSFET with oxide charge balance region in active area and junction balance region in termination area is disclosed. The inventive structure can reduce specific on-resistance and enhance avalanche capability. The device structure is achieved using angle implant of N and P columns.

Abstract: A trench MOSFET is disclosed having shielded trenched gates in active area, multiple floating trenched gates and at least one channel stop trenched gate in termination area. A semiconductor power device layout is disclosed consisting of at least two said trench MOSFETs connected together with multiple sawing trenched gates across a space between the two trench MOSFETs having a width same as scribe line, making the invented trench MOSFET be feasibly achieved without degraded performance.

Abstract: A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed, wherein: the shielded gate structure comprises a first poly-silicon layer to serve as a shielded electrode and a second poly-silicon layer to serve as a gate electrode, and the ESD clamp diode formed between two protruding electrodes is also formed by the first poly-silicon layer. A mask specially used to define the ESD clamp diode portion is saved.

Abstract: A wheel cover of an aluminum alloy wheel is revealed. The wheel cover is located on and covered an outer side of the aluminum alloy wheel. A peripheral wall is axially extended from a circumference of a central insertion hole of the wheel cover. The peripheral wall is fitted into a central insertion hole of the aluminum alloy wheel. A locking part on each spring arranged around the peripheral wall is locked with an inner edge of the insertion hole of the aluminum alloy wheel. The production of the aluminum alloy wheel is generally based on the central insertion hole thereof. The wheel cover and the insertion hole are connected mainly at the central insertion hole owing to precision of the size and position of the central insertion hole. Thereby the wheel cover and the aluminum alloy wheel are assembled conveniently.

Abstract: A trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.

Abstract: A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed, wherein: the shielded gate structure comprises a first poly-silicon layer to serve as a shielded electrode and a second poly-silicon layer to serve as a gate electrode, and the ESD clamp diode formed between two protruding electrodes is also formed by the first poly-silicon layer. A mask specially used to define the ESD clamp diode portion is saved.

Abstract: A method for manufacturing a super junction trench MOSFET by growing a first epitaxial layer of a first conductivity type upon a heavily doped substrate layer of a first conductivity type; forming a deep trench mask covering a top surface of the first epitaxial layer; applying a trench mask to form a deep trench extending into the substrate layer by successively dry oxide etch and dry silicon etch; and carrying out angle ion implantations of the first conductivity type dopant and driving-in to form a first type column regions with column shape within the first epitaxial layer; and carrying out angle ion implantations of a second conductivity type dopant and diffusion to form a second type column regions with column shape adjacent to sidewalls of the deep trench, in parallel with and surrounding the first type column regions; and removing the hard mask.

Abstract: A trench MOSFET with diffused drift region and closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.

Abstract: A super-junction trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are at least formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.

Abstract: A super-junction trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are at least formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.

Abstract: A super-junction trench MOSFET with closed cell layout is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell. Trenched source-body contacts are disposed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.

Abstract: A super-junction trench MOSFET integrated with embedded trench Schottky rectifier is disclosed for soft reverse recovery operation. The embedded trench Schottky rectifier can be integrated in a same unit cell with the super-junction trench MOSFET.