Patents by Inventor Fu-Yuan Hsieh

Fu-Yuan Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Super-junction trench MOSFET structure
    Patent number: 9293527
    Abstract: A super-junction trench MOSFET is disclosed by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches with buried voids in each unit cell for super-junction. A buffer poly-silicon layer is deposited above the buried void for stress release to prevent wafer crack and silicon defects.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 22, 2016
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • SUPER-JUNCTION STRUCTURES HAVING IMPLANTED REGIONS SURROUNDING AN N EPITAXIAL LAYER IN DEEP TRENCH
    Publication number: 20150318379
    Abstract: A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier.
    Type: Application
    Filed: July 15, 2015
    Publication date: November 5, 2015
    Inventor: FU-YUAN HSIEH
  • TRENCH MOSFET WITH SELF-ALIGNED SOURCE AND CONTACT REGIONS USING THREE MASKS PROCESS
    Publication number: 20150221733
    Abstract: A trench MOSFET structure having self-aligned features for mask saving and on-resistance reduction is disclosed, wherein source regions are formed by performing source Ion Implantation through contact holes of a contact interlayer in the middle of adjacent terrace trenched gates, and further source diffusion. Both the contact holes and source regions are self-aligned to the terrace trenched gates.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: FU-YUAN HSIEH
  • Super-junction structures having implanted regions surrounding an N epitaxial layer in deep trench
    Patent number: 9099320
    Abstract: A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: August 4, 2015
    Assignee: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Avalanche capability improvement in power semiconductor devices using three masks process
    Patent number: 9018701
    Abstract: A power semiconductor device with improved avalanche capability is disclosed by forming at least one avalanche capability enhancement doped region underneath an ohmic contact doped region. Moreover, a source mask is saved by using three masks process and the avalanche capability is further improved.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: April 28, 2015
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Super-junction trench MOSFETs with short terminations
    Patent number: 9000515
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: April 7, 2015
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Super-junction trench MOSFETs with short terminations
    Patent number: 8999789
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 7, 2015
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • SUPER-JUNCTION STRUCTURES HAVING IMPLANTED REGIONS SURROUNDING AN N EPITAXIAL LAYER IN DEEP TRENCH
    Publication number: 20150076594
    Abstract: A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: FU-YUAN HSIEH
  • SUPER-JUNCTION TRENCH MOSFETS WITH SHORT TERMINATIONS
    Publication number: 20150037954
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventor: FU-YUAN HSIEH
  • High switching trench MOSFET
    Patent number: 8907415
    Abstract: A shielded gate trench metal oxide semiconductor filed effect transistor (MOSFET) having high switching speed is disclosed. The inventive shielded gate trench MOSFET includes a shielded electrode spreading resistance placed between a shielded gate electrode and a source metal to enhance the performance of the shielded gate trench MOSFET by adjusting doping concentration of poly-silicon in gate trenches to a target value. Furthermore, high cell density is achieved by employing the inventive shielded gate trench MOSFET without requirement of additional cost.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: December 9, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • SUPER-JUNCTION TRENCH MOSFETS WITH SHORT TERMINATIONS
    Publication number: 20140346593
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: FU-YUAN HSIEH
  • Trench MOSFET having a top side drain
    Patent number: 8889514
    Abstract: This invention discloses a trench MOSFET comprising a top side drain region in a wide trench in a termination area besides a BV sustaining area, wherein said top side drain comprises a top drain metal connected to an epitaxial layer and a substrate through a plurality of trenched drain contacts, wherein the wide trench is formed simultaneously when a plurality of gate trenches are formed in an active area, and the trenched drain contacts are formed simultaneously when a trenched source-body contact is formed in the active area.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: November 18, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Trench MOSFET with trenched floating gates having thick trench bottom oxide as termination
    Patent number: 8889513
    Abstract: A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 18, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • TRENCH MOSFET STRUCTURE HAVING SELF-ALIGNED FEATURES FOR MASK SAVING AND ON-RESISTANCE REDUCTION
    Publication number: 20140291753
    Abstract: A trench MOSFET structure having self-aligned features for mask saving and on-resistance reduction is disclosed, wherein the source region is formed by performing source Ion Implantation through contact opening of a contact interlayer, and further source diffusion. A dielectric sidewall spacer is formed on sidewalls of the contact interlayer in the contact open areas to define trenched source-body contacts for on-resistance reduction and avalanche capability improvement.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 2, 2014
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: FU-YUAN HSIEH
  • Fast switching super-junction trench MOSFETs
    Patent number: 8829607
    Abstract: A fast switching super-junction trench MOSFET is disclosed having a floating region formed underneath each gate trench and surrounding at least bottom of each the gate trench, which has a parasitic body diode with superior reverse recovery characteristics.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: September 9, 2014
    Assignees: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Shielded gate MOSFET-Schottky rectifier-diode integrated circuits with trenched contact structures
    Patent number: 8816348
    Abstract: A trench shielded gate MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage, lower cost and improved performance. The present semiconductor device achieve low Vf and reverse leakage current for embedded Schottky rectifier, having over-voltage protection and avalanche protection between gate and source and between gate and drain.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: August 26, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH EMBEDDED SCHOTTKY RECTIFIER USING REDUCED MASKS PROCESS
    Publication number: 20140213026
    Abstract: A trench MOSFET with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches.
    Type: Application
    Filed: April 3, 2014
    Publication date: July 31, 2014
    Inventor: Fu-Yuan HSIEH
  • TOUCH-SENSITIVE ELECTRONIC DEVICE AND METHOD FOR CONTROLLING APPLICATIONS USING EXTERNAL KEYPAD
    Publication number: 20140176471
    Abstract: For a touch-sensitive electronic device with a touch screen, a method allows user operations on a connected peripheral input device such as an external keypad to be mapped to, and activate, keys displayed or inbuilt on the electronic device. Each key of the external keypad is initialized when the external keypad is connected to the electronic device. The user selects an application to be controlled and a coordinate position for each displayed or inbuilt key is associated with the keys of the external keypad. The electronic device receives a sensing signal when a key of the external keypad is pressed, determines a coordinate position of the associated key on the touch screen, and executes an operation of the application accordingly.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 26, 2014
    Applicant: CHIUN MAI COMMUNICATION SYSTEMS, INC.
    Inventor: FU-YUAN HSIEH
  • Trench MOSFET with trenched floating gates having thick trench bottom oxide as termination
    Patent number: 8759910
    Abstract: A semiconductor power device with trenched floating gates having thick bottom oxide as termination is disclosed. The gate charge is reduced by forming a HDP oxide layer padded by a thermal oxide layer on trench bottom and a top surface of mesa areas between adjacent trenched gates. Therefore, only three masks are needed to achieve the device structure.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: June 24, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • SHORT CHANNEL TRENCH MOSFETS
    Publication number: 20140159149
    Abstract: A trench MOSFET with a short channel length is disclosed for reducing channel resistance, wherein at least one field relief region is formed underneath the body region in an epitaxial layer between every two adjacent gate trenches and self-aligned with a trenched source-body contact for prevention of drain/source punch-through issue.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan HSIEH