Patents by Inventor Fu-Yuan Hsieh

Fu-Yuan Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TRENCH MOSFET STRUCTURES USING THREE MASKS PROCESS
    Publication number: 20130299901
    Abstract: A trench MOSFET comprising a plurality of trenched gates surrounded by source regions encompassed in body regions in active area. A plurality of trenched source-body contact structure penetrating through the source regions and extending into the body regions, are filled with tungsten plugs padded with a Ti layer, a first and a second TiN layer, wherein the second TiN layer is deposited after Ti silicide formation to avoid W spiking occurrence.
    Type: Application
    Filed: July 24, 2013
    Publication date: November 14, 2013
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: FU-YUAN HSIEH
  • Super-junction trench MOSFET having deep trenches with buried voids
    Patent number: 8575690
    Abstract: A super-junction trench MOSFET is disclosed for high voltage device by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches with buried voids in each unit cell for super-junction. Meanwhile, at least one trenched gate and multiple trenched source-body contacts are formed in each unit cell between the pair of deep trenches.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: November 5, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • MOSFET-Schottky rectifier-diode integrated circuits with trench contact structures
    Patent number: 8569765
    Abstract: A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for Gate-Source clamp diode and avalanche protection for Gate-Drain clamp diode.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: October 29, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Semiconductor power device with embedded diodes and resistors using reduced mask processes
    Patent number: 8569780
    Abstract: A trench semiconductor power device integrated with a Gate-Source and a Gate-Drain clamp diodes without using source mask is disclosed, wherein a plurality source regions of a first conductivity type of the trench semiconductor device and multiple doped regions of the first conductivity type of the clamp diodes are formed simultaneously through contact open areas defined by a contact mask.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: October 29, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Super-junction trench MOSFET with multiple trenched gates in unit cell
    Patent number: 8564058
    Abstract: A super-junction trench MOSEET is disclosed for high voltage device by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches in each unit cell for super-junction. Meanwhile, at least one trenched gate and multiple trenched source-body contacts are formed in each unit cell between the pair of deep trenches.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: October 22, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Semiconductor power devices integrated with a trenched clamp diode
    Patent number: 8564047
    Abstract: A semiconductor power device having shielded gate structure integrated with a trenched clamp diode formed in a semiconductor silicon layer, wherein the shielded gate structure comprises a shielded electrode formed by a first poly-silicon layer and a gate electrode formed by a second poly-silicon layer. The trenched clamp diode is formed by the first poly-silicon layer. A shielded gate mask used to define the shielded gate is also used to define the trenched clamp diode. Therefore, one poly-silicon layer and a mask for the trenched clamp diode are saved.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: October 22, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Trench semiconductor power device having active cells under gate metal pad
    Patent number: 8564054
    Abstract: A trench semiconductor power device having active cells under gate metal pad to increase total active area for lowering on-resistance is disclosed. The gate metal pad is not only for gate wire bonding but also for active cells disposition. Therefore, the device die can be shrunk so that the number of devices per wafer is increased for die cost reduction. Moreover, the device can be packaged into smaller type package for further cost reduction.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: October 22, 2013
    Assignee: Feei Cherng Enterprise Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Trench MOSFET with trenched floating gates in termination
    Patent number: 8564052
    Abstract: A trench MOSFET comprising a plurality of transistor cells, multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in active area. In some preferred embodiments, the trench MOSFET further comprises a gate metal runner surrounding outside the source metal and extending to the gate metal pad. Furthermore, the termination area further comprises an EPR surrounding outside the trenched floating gates.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: October 22, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Method for manufacturing a power semiconductor device
    Patent number: 8563381
    Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: October 22, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Trench MOSFET with trenched floating gates in termination
    Patent number: 8564053
    Abstract: A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area. The trench MOSFET further comprise an EPR surrounding outside the multiple trenched floating gates in the termination area.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: October 22, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • TRENCH MOSFET WITH SHIELDED ELECTRODE AND AVALANCHE ENHANCEMENT REGION
    Publication number: 20130256786
    Abstract: A trench MOSFET with shielded electrode and improved avalanche enhancement region is disclosed. The inventive structure can achieve a better avalanche capability by applying an improved avalanche enhancement region having a same doping concentration as the epitaxial layer where said trench MOSFET is formed without increasing Rds.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Applicant: FEEI CHERNG ENTERPRISE CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • SEMICONDUCTOR POWER DEVICE INTEGRATED WITH CLAMP DIODES HAVING DOPANT OUT-DIFFUSION SUPPRESSION LAYERS
    Publication number: 20130234237
    Abstract: A semiconductor power device integrated with clamp diodes is disclosed by offering dopant out-diffusion suppression layers to enhance the ESD protection between gate and source, and avalanche capability between drain and source.
    Type: Application
    Filed: March 12, 2012
    Publication date: September 12, 2013
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • SEMICONDUCTOR POWER DEVICE INTEGRATED WITH ESD PROTECTION DIODES
    Publication number: 20130234238
    Abstract: A semiconductor power device integrated with ESD protection diode is disclosed by offering a dopant out-diffusion suppression layers prior to source dopant activation or diffusion to enhance ESD protection capability between gate and source.
    Type: Application
    Filed: July 6, 2012
    Publication date: September 12, 2013
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • Method of manufacturing trench MOSFET structures using three masks process
    Patent number: 8530313
    Abstract: In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 10, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Trench MOSFET with trenched floating gates having thick trench bottom oxide as termination
    Patent number: 8525255
    Abstract: A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 3, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Trench MOSFET with trenched floating gates and trenched channel stop gates in termination
    Patent number: 8519477
    Abstract: A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The multiple trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area. The trench MOSFET further comprises at least one trenched channel stop gate around outside of the trenched floating gates and connected to at least one sawing trenched gate extended into scribe line for prevention of leakage path formation between drain and source regions.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 27, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • TRENCH MOSFET HAVING A TOP SIDE DRAIN
    Publication number: 20130207172
    Abstract: This invention discloses a trench MOSFET comprising a top side drain region in a wide trench in a termination area besides a BV sustaining area, wherein said top side drain comprises a top drain metal connected to an epitaxial layer and a substrate through a plurality of trenched drain contacts, wherein the wide trench is formed simultaneously when a plurality of gate trenches are formed in an active area, and the trenched drain contacts are formed simultaneously when a trenched source-body contact is formed in the active area.
    Type: Application
    Filed: February 13, 2012
    Publication date: August 15, 2013
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • Trench MOSFET layout with trenched floating gates and trenched channel stop gates in termination
    Patent number: 8487372
    Abstract: A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of dual trench MOSFETs connected together with multiple sawing trenched gates across a space between the two trench MOSFETs having a width same as scribe line.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: July 16, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • SEMICONDUCTOR POWER DEVICE HAVING IMPROVED TERMINATION STRUCTURE FOR MASK SAVING
    Publication number: 20130168761
    Abstract: A improved termination structure for semiconductor power devices is disclosed, comprising a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide termination trench by doing poly-silicon CMP so that body ion implantation is blocked by the trenched field plate on the trench bottom to prevent a body region formation underneath the trench bottom of the wide termination trench, degrading avalanche voltage.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: FEEI CHERNG ENTERPRISE CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • TRENCH SEMICONDUCTOR POWER DEVICE HAVING ACTIVE CELLS UNDER GATE METAL PAD
    Publication number: 20130168764
    Abstract: A trench semiconductor power device having active cells under gate metal pad to increase total active area for lowering on-resistance is disclosed. The gate metal pad is not only for gate wire bonding but also for active cells disposition. Therefore, the device die can be shrunk so that the number of devices per wafer is increased for die cost reduction. Moreover, the device can be packaged into smaller type package for further cost reduction.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: FEEI CHERNG ENTERPRISE CO., LTD.
    Inventor: Fu-Yuan HSIEH