Patents by Inventor Fu-Yuan (Max) Hsu

Fu-Yuan (Max) Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120113364
    Abstract: A display panel is provided. The display panel includes a first substrate and a second substrate. The second substrate comprises a center region, a first border region and a second border region. The center region has a first center region edge and a second center region edge. The center region corresponds to an active area for displaying an image of the display panel. The first border region, adjacent to the center region and located outside the first center region edge, has a first border region edge. The second border region, adjacent to the center region and located outside the second center region edge, has a second border region edge. The distance between the first center region edge and the first border region edge is larger than the distance between the second center region edge and the second border region edge.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 10, 2012
    Applicant: CHIMEI INNOLUX CORPORATION
    Inventors: Fu-Yuan HSUEH, Tzu-Yu CHENG
  • Publication number: 20120105986
    Abstract: A housing structure for miniature lens focus module has a top portion formed into a stepped structure, that is, the housing has a size-reduced topmost portion relative to the rest rear portion thereof and has a shoulder portion formed therein, so that a plate-shaped spring element for holding a lens holder can be directly connected to the shoulder portion in the housing to keep away from the topmost portion of the housing by a predetermined distance and define an operation space between the shoulder portion and the topmost portion, allowing the lens holder and accordingly a lens held thereto to axially linearly move within the operation space to focus light. The spacer provided in the prior art lens focus module can be omitted to reduce the cost and the assembling procedures of the lens focus module.
    Type: Application
    Filed: November 1, 2010
    Publication date: May 3, 2012
    Inventors: Fu-Yuan Wu, Shang-Yu Hsu
  • Patent number: 8169209
    Abstract: An output driving circuit capable of reducing EMI effect includes a non-overlapping signal generation unit for generating a first non-overlapping signal and a second non-overlapping signal according to an input signal, a pre-driver for generating a first pre-driving signal and a second pre-driving signal according to the first non-overlapping signal and the second non-overlapping signal, a high-side switch, a low-side switch, and a control unit for controlling the high-side switch or the low-side switch to be switched into a weak on state to reduce load inductive current effect for a load.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: May 1, 2012
    Assignee: Anpec Electronics Corporation
    Inventors: Fu-Yuan Chen, Yu-Chen Chiang, Ming-Hung Chang
  • Publication number: 20120099201
    Abstract: A tilt-type anti-shake compensation structure for auto-focus module includes an auto-focus module having a lens assembly held thereto and driving the latter to move forward and rearward in a light entering path, i.e. in z-axis direction, so as to focus a captured image; an outer frame enclosing the auto-focus module therein, and having an elastic supporting member provided therein to connect to and between upper ends of the outer frame and the auto-focus module; and a compensation driving unit arranged behind the auto-focus module for driving the auto-focus module to tilt leftward and rightward on x-axis, or forward and rearward on y-axis, within the outer frame, so as to compensate any image deviation due to shake caused by hands. The anti-shake structure is simple and can quickly compensate shake caused by hands.
    Type: Application
    Filed: October 22, 2010
    Publication date: April 26, 2012
    Inventors: Yi-Liang Chan, Chao-Chang Hu, Fu-Yuan Wu
  • Patent number: 8164162
    Abstract: A structure of power semiconductor device integrated with clamp diodes sharing same gate metal pad is disclosed. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: April 24, 2012
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8164114
    Abstract: A semiconductor power device integrated with a Gate-Source ESD diode for providing an electrostatic discharge (ESD) protection and a Gate-Drain clamp diode for drain-source avalanche protection. The semiconductor power device further includes a Nitride layer underneath the diodes and a thick oxide layer as an etching stopper layer for protecting a thin oxide layer on top surface of body region from over-etching.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: April 24, 2012
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8164139
    Abstract: A trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) structure with guard ling, includes: a substrate including an epi layer region on the top thereof a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; and a guard ring wrapping around the trench gates with contact metal plug underneath the gate metal layer.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 24, 2012
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20120080748
    Abstract: A trench MOSFET with short channel length and super pinch-off regions is disclosed, wherein the super pinch-off regions are implemented by forming at least two type pinch-off regions for punch-through prevention: a first type pinch-off region with a wide mesa width generated between lower portion of two adjacent trenched gates and below an anti-punch through region surrounding bottom of a trenched source-body contact filled with metal plug; a second type pinch-off region with a narrow mesa width generated below a body region and between upper portion of one trenched gate and the anti-punch-through region along sidewall of the trenched source-body contact.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • Patent number: 8148773
    Abstract: A structure of power semiconductor device integrated with clamp diodes having separated gate metal pad is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon or gate metal.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: April 3, 2012
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20120074489
    Abstract: A super-junction trench MOSFET with Resurf Stepped Oxide and trenched contacts is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . Furthermore, the fabrication method can be implemented more reliably with lower cost.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 29, 2012
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • Publication number: 20120064684
    Abstract: A method of manufacturing a super junction semiconductor device having resurf stepped oxide structure is disclosed by providing semiconductor silicon layer having trenches and mesas. A plurality of first doped column regions of a second conductivity type in parallel surrounded with second doped column regions of a first conductivity type adjacent to sidewalls of the trenches are formed by angle ion implantations into a plurality of mesas through opening regions in a block layer covering both the mesas and a termination area.
    Type: Application
    Filed: November 18, 2011
    Publication date: March 15, 2012
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • Publication number: 20120061754
    Abstract: A super-junction trench MOSFET with Resurf Stepped Oxide and split gate electrodes is disclosed. The inventive structure can apply additional freedom for better optimization of device performance and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. Furthermore, the fabrication method can be implemented more reliably with lower cost.
    Type: Application
    Filed: November 23, 2011
    Publication date: March 15, 2012
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • Publication number: 20120062542
    Abstract: An LCD panel with function of compensating feed-through effect includes plural groups of pixels, a gate-driving circuit, a data-driving circuit, and a gamma voltage generator. Each group of pixels includes first pixel and second pixel. The first pixel and the second pixel share a data line, and are respectively coupled to first gate line and second gate line. When the gate-driving circuit drives the first gate line, the gamma voltage generator provides un-compensated gamma voltages for the data-driving circuit writing data to the first pixel. When the gate-driving circuit drives the first and the second gate lines at the same time, the gamma voltage generator provides gamma voltages compensated by a compensating voltage level for the data-driving circuit writing data to the second pixel. In this way, the feed-through effect suffered by the second pixel is compensated, so that each pixel of the LCD panel can display with correct brightness.
    Type: Application
    Filed: November 17, 2010
    Publication date: March 15, 2012
    Inventors: Fu-Yuan Liou, Shu-Huan Hsieh, Chung-Lung Li
  • Patent number: 8132313
    Abstract: An inspecting circuit layout according to the present invention is provided. The inspecting circuit layout is adapted for inspecting panel units group by group, each of the panel units having a plurality of first and second signal lines. The inspecting circuit layout includes a multiplexer (MUX) and an inspecting pad. The MUX is electrically connected with at least one of the first or second signal lines of the panel units, and the inspecting pad is electrically connected to the MUX. The MUX is adapted for selectively connecting the inspecting pad with the first or second signal lines of a group of panel units.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: March 13, 2012
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Fu-Yuan Shiau, Chih-Yu Chen, Meng-Chi Liou
  • Publication number: 20120056865
    Abstract: A light emitting diode (LED) driving apparatus is provided, which includes a power conversion circuit for receiving and converting an input power so as to generate a DC voltage to simultaneously drive a plurality of LED strings arranged in parallel; and a plurality of current regulation chips each having a single regulation channel and respectively corresponding to the LED strings, wherein an ith current regulation chip is only used for regulating a current flowing through an ith LED string, where i is a positive integer.
    Type: Application
    Filed: December 6, 2010
    Publication date: March 8, 2012
    Applicant: POWER FOREST TECHNOLOGY CORPORATION
    Inventors: Fu-Yuan Shih, Yang-Tai Tseng
  • Patent number: 8125462
    Abstract: The present invention relates to a projecting capacitive touch sensing device, display panel, and image display system. The projecting capacitive touch sensing comprises an array of a plurality of sensing units, each sensing unit including: a first electrode made of a sensing material, at least one second electrode made of a sensing material and being disposed around the peripheral of the first electrode, at least one first sensing axis electrically connected to the first electrode, and at least one second sensing axis electrically connected to the second electrodes. The first electrode is quadrangle, while the second electrodes are triangular-shaped. The first electrode and the plurality of second electrodes are arranged to form a rectangular, and a non-sensing area is defined between the first electrode and the second electrodes.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: February 28, 2012
    Assignee: Chimei Innolux Corporation
    Inventors: Wei-Cheng Lin, Kai-Chieh Yang, Fu-Yuan Hsueh, Ting-Kuo Chang
  • Patent number: 8120106
    Abstract: A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: February 21, 2012
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8115754
    Abstract: A data line driving method adapted in a display panel driver circuit is provided. The display panel driver circuit comprises a plurality rows of gate lines and a plurality of data driver stages each corresponding to a data line group, wherein the data line driving method comprises the steps of: turning on the data driver stages in a first sequential order to input a first frame data in the data line groups corresponding to the data driver stages in each gate line activation time within a first frame period; and turning on the data driver stages in a second sequential order which is opposed to the first sequential order to input a second frame data in the data line groups corresponding to the data driver stages in each gate line activation time within a second frame period; wherein the first and the second frame period are two interlaced periods next to each other.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: February 14, 2012
    Assignee: Au Optronics Corporation
    Inventors: Chung-Lin Fu, Fu-Yuan Liou, Yu-Hsin Ting, Shu-Huan Hsieh
  • Publication number: 20120032261
    Abstract: A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.
    Type: Application
    Filed: October 20, 2011
    Publication date: February 9, 2012
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • Patent number: D654043
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: February 14, 2012
    Assignee: Motorola Mobility, Inc.
    Inventors: Ed Pan, Ruben D. Castano, Fu-Yuan Hsu