Patents by Inventor Fu-Yuan (Max) Hsu

Fu-Yuan (Max) Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130271682
    Abstract: An LCD panel with function of compensating feed-through effect includes plural groups of pixels, a gate-driving circuit, a data-driving circuit, and a gamma voltage generator. Each group of pixels includes first pixel and second pixel. The first pixel and the second pixel share a data line, and are respectively coupled to first gate line and second gate line. When the gate-driving circuit drives the first gate line, the gamma voltage generator provides un-compensated gamma voltages for the data-driving circuit writing data to the first pixel. When the gate-driving circuit drives the first and the second gate lines at the same time, the gamma voltage generator provides gamma voltages compensated by a compensating voltage level for the data-driving circuit writing data to the second pixel. In this way, the feed-through effect suffered by the second pixel is compensated, so that each pixel of the LCD panel can display with correct brightness.
    Type: Application
    Filed: June 10, 2013
    Publication date: October 17, 2013
    Inventors: Fu-Yuan Liou, Shu-Huan Hsieh, Chung-Lung Li
  • Publication number: 20130256786
    Abstract: A trench MOSFET with shielded electrode and improved avalanche enhancement region is disclosed. The inventive structure can achieve a better avalanche capability by applying an improved avalanche enhancement region having a same doping concentration as the epitaxial layer where said trench MOSFET is formed without increasing Rds.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Applicant: FEEI CHERNG ENTERPRISE CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • Publication number: 20130234237
    Abstract: A semiconductor power device integrated with clamp diodes is disclosed by offering dopant out-diffusion suppression layers to enhance the ESD protection between gate and source, and avalanche capability between drain and source.
    Type: Application
    Filed: March 12, 2012
    Publication date: September 12, 2013
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • Publication number: 20130234238
    Abstract: A semiconductor power device integrated with ESD protection diode is disclosed by offering a dopant out-diffusion suppression layers prior to source dopant activation or diffusion to enhance ESD protection capability between gate and source.
    Type: Application
    Filed: July 6, 2012
    Publication date: September 12, 2013
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • Patent number: 8531534
    Abstract: A lens driving apparatus comprises a lens portion having at least one lens (21), a first driving portion (39) to cause a movement of said lens portion relatively to a base portion (40) along a vertical direction of a light axis (L) of said lens portion, and a second driving portion (38) to cause a movement of said lens portion relatively to said base portion along said light axis.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: September 10, 2013
    Assignee: TDK Taiwan Corp.
    Inventors: Chao-Chang Hu, Fu-Yuan Wu, Yi-Lang Chan
  • Patent number: 8530313
    Abstract: In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 10, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8525255
    Abstract: A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 3, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8525764
    Abstract: An LCD panel with function of compensating feed-through effect includes plural groups of pixels, a gate-driving circuit, a data-driving circuit, and a gamma voltage generator. Each group of pixels includes first pixel and second pixel. The first pixel and the second pixel share a data line, and are respectively coupled to first gate line and second gate line. When the gate-driving circuit drives the first gate line, the gamma voltage generator provides un-compensated gamma voltages for the data-driving circuit writing data to the first pixel. When the gate-driving circuit drives the first and the second gate lines at the same time, the gamma voltage generator provides gamma voltages compensated by a compensating voltage level for the data-driving circuit writing data to the second pixel. In this way, the feed-through effect suffered by the second pixel is compensated, so that each pixel of the LCD panel can display with correct brightness.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: September 3, 2013
    Assignee: AU Optronics Corp.
    Inventors: Fu-Yuan Liou, Shu-Huan Hsieh, Chung-Lung Li
  • Patent number: 8519477
    Abstract: A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The multiple trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area. The trench MOSFET further comprises at least one trenched channel stop gate around outside of the trenched floating gates and connected to at least one sawing trenched gate extended into scribe line for prevention of leakage path formation between drain and source regions.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 27, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20130215511
    Abstract: An elastic supporting structure for an optical image stabilizer is provided. The optical image stabilizer includes a movable portion, a compensation module, and a plurality of suspension wires. The movable portion is provided therein with a lens. The compensation module corresponds to the movable portion, and both are located on the same image-capturing optical axis. Each suspension wire has two ends respectively connected to the movable portion and the compensation module. The movable portion is provided with an upper spring plate. One end of each suspension wire is connected to a length-increased outer line element and at least one additional auxiliary line element of the upper spring plate, and the other end of each suspension wire is connected to the compensation module, such that the movable portion corresponds to the compensation module and is spaced therefrom by a predetermined distance. Also, anti-shake function performs well with suspension wires.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Applicant: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Shih-Ting Huang, Jyun-Jie Lin
  • Publication number: 20130207172
    Abstract: This invention discloses a trench MOSFET comprising a top side drain region in a wide trench in a termination area besides a BV sustaining area, wherein said top side drain comprises a top drain metal connected to an epitaxial layer and a substrate through a plurality of trenched drain contacts, wherein the wide trench is formed simultaneously when a plurality of gate trenches are formed in an active area, and the trenched drain contacts are formed simultaneously when a trenched source-body contact is formed in the active area.
    Type: Application
    Filed: February 13, 2012
    Publication date: August 15, 2013
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • Patent number: 8487372
    Abstract: A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of dual trench MOSFETs connected together with multiple sawing trenched gates across a space between the two trench MOSFETs having a width same as scribe line.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: July 16, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20130168761
    Abstract: A improved termination structure for semiconductor power devices is disclosed, comprising a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide termination trench by doing poly-silicon CMP so that body ion implantation is blocked by the trenched field plate on the trench bottom to prevent a body region formation underneath the trench bottom of the wide termination trench, degrading avalanche voltage.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: FEEI CHERNG ENTERPRISE CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • Publication number: 20130168760
    Abstract: A trench MOSFET with split gates and diffused drift region for on-resistance reduction is disclosed. Each of the split gates is symmetrically disposed in the middle of the source electrode and adjacent trench sidewall of a deep trench. The inventive structure can save a mask for definition of the location of the split gate electrodes. Furthermore, the fabrication method can be implemented more reliably with lower cost.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • Publication number: 20130168764
    Abstract: A trench semiconductor power device having active cells under gate metal pad to increase total active area for lowering on-resistance is disclosed. The gate metal pad is not only for gate wire bonding but also for active cells disposition. Therefore, the device die can be shrunk so that the number of devices per wafer is increased for die cost reduction. Moreover, the device can be packaged into smaller type package for further cost reduction.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: FEEI CHERNG ENTERPRISE CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • Patent number: 8477129
    Abstract: A system for displaying images is provided. The system comprises a reference voltage source, a digital-to-analog converter, a multiplier and a buffer. The reference voltage source outputs a voltage signal, wherein the magnitude of the voltage signal is 1/N of a driving voltage. The digital-to-analog converter converts the voltage signal to a first voltage. The multiplier receives and multiplies the first voltage by N to output the driving voltage. The buffer receives the driving voltage to drive a data line.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: July 2, 2013
    Assignee: TPO Displays Corp.
    Inventors: Fu-Yuan Hsueh, Kai-Chieh Yang
  • Patent number: 8466514
    Abstract: A trench semiconductor power device integrated with four types of ESD clamp diodes for optimization of total perimeter of the ESD clamp diodes, wherein the ESD clamp diodes comprise multiple back to back Zener diodes with alternating doped regions of a first conductivity type next to a second conductivity type, wherein each of the doped regions has a closed ring structure.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: June 18, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: D683727
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: June 4, 2013
    Assignee: Motorola Mobility LLC
    Inventors: Lei Xia, Ruben D Castano, Wei-Wei Chen, Fu-Yuan Hsu
  • Patent number: D683728
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: June 4, 2013
    Assignee: Motorola Mobility LLC
    Inventors: Lei Xia, Ruben D Castano, Fu-Yuan Hsu
  • Patent number: D687406
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: August 6, 2013
    Assignee: Motorola Mobility LLC
    Inventors: Lei Xia, Ruben D. Castano, Fu-Yuan Hsu, Vincent Kenya Shyu