Patents by Inventor Fusen Chen
Fusen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6974771Abstract: In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects.Type: GrantFiled: July 20, 2004Date of Patent: December 13, 2005Assignee: Applied Materials, Inc.Inventors: Fusen Chen, Ling Chen, Walter Benjamin Glenn, Praburam Gopalraja, Jianming Fu
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Publication number: 20050272254Abstract: We have discovered a method of providing a thin approximately from about 2 ? to about 100 ? thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 ?? cm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.Type: ApplicationFiled: July 18, 2005Publication date: December 8, 2005Applicant: Applied Materials, Inc.Inventors: Peijun Ding, Zheng Xu, Hong Zhang, Xianmin Tang, Praburam Gopalraja, Suraj Rengarajan, John Forster, Jianming Fu, Tony Chiang, Gongda Yao, Fusen Chen, Barry Chin, Gene Kohara
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Publication number: 20050266682Abstract: In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects.Type: ApplicationFiled: July 19, 2005Publication date: December 1, 2005Inventors: Fusen Chen, Ling Chen, Walter Glenn, Praburam Gopalraja, Jianming Fu
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Publication number: 20050255691Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target.Type: ApplicationFiled: July 19, 2005Publication date: November 17, 2005Inventors: Peijun Ding, Rong Tao, Zheng Xu, Daniel Lubben, Suraj Rengarajan, Michael Miller, Arvind Sundarrajan, Xianmin Tang, John Forster, Jianming Fu, Roderick Mosely, Fusen Chen, Praburam Gopalraja
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Publication number: 20050255700Abstract: A multi-step sputtering process in plasma sputter reactor having target and magnetron operable in two modes, for example, in a substrate sputter etch and a substrate sputter deposition. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process with the inventive reactor or other reactor includes a first step of highly ionized sputter deposition of copper, which can optionally be used to remove the barrier layer at the bottom of the via, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and a third step of electroplating copper into the hole to complete the metallization. The first two steps can be also used with barrier metals.Type: ApplicationFiled: June 24, 2005Publication date: November 17, 2005Inventors: Praburam Gopalraja, Jianming Fu, Fusen Chen, Girish Dixit, Zheng Xu, Wei Wang, Ashok Sinha
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Publication number: 20050208767Abstract: We have discovered a method of providing a thin, approximately from about 2 ? to about 100 ? thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 ??cm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface to form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.Type: ApplicationFiled: February 28, 2005Publication date: September 22, 2005Inventors: Peijun Ding, Zheng Xu, Hong Zhang, Xianmin Tang, Praburam Gopalraja, Suraj Rengarajan, John Forster, Jianming Fu, Tony Chiang, Gongda Yao, Fusen Chen, Barry Chin, Gene Kohara
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Patent number: 6913680Abstract: A method and associated apparatus includes depositing metal on a plating surface of an object immersed in an electrolyte solution prior to bulk deposition on the plating surface. In one aspect, the method further includes applying a voltage between an anode and the plating surface to enhance the concentration of metal ions in the electrolyte solution that is contained in a feature on the plating surface prior to the bulk deposition on the plating surface.Type: GrantFiled: July 12, 2000Date of Patent: July 5, 2005Assignee: Applied Materials, Inc.Inventors: Bo Zheng, Hougong Wang, Girish Dixit, Fusen Chen
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Patent number: 6899796Abstract: A two-step method of filling copper into a high-aspect ratio via or dual-damascene structure. The first step sputters at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole. The initial copper sputtering is preferably performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter resulting overhangs from the corners while depositing deep in the hole. The second step may include either electrochemical plating or sputtering performed at a higher temperature, e.g., at least 200° C. and with lower wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma.Type: GrantFiled: May 1, 2003Date of Patent: May 31, 2005Assignee: Applied Materials, Inc.Inventors: Wei D. Wang, Anantha K. Subramani, Jianming Fu, Praburam Gopalraja, Jick M. Yu, Fusen Chen
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Patent number: 6884329Abstract: A method of filling copper into a high-aspect ratio via by a plasma sputter process and allowing the elimination of electrochemical plating. In one aspect of the invention, the sputtering is divided into a first step performed at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole, and a second step performed at a higher temperature, e.g., at least 200° C. and with at least portions of low wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma. In still another aspect, copper sputtering, even in the final fill phase, is performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter from the corners.Type: GrantFiled: January 10, 2003Date of Patent: April 26, 2005Assignee: Applied Materials, Inc.Inventors: Wei D. Wang, Anantha K. Subramani, Jianming Fu, Praburam Gopalraja, Jick M. Yu, Fusen Chen
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Publication number: 20050085068Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper.Type: ApplicationFiled: November 3, 2004Publication date: April 21, 2005Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen Chen, Barry Chin, Gene Kohara, Zheng Xu, Hong Zhang
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Publication number: 20050056536Abstract: A multi-step sputtering process in plasma sputter reactor having target and magnetron operable in two modes, for example, in a substrate sputter etch and a substrate sputter deposition. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process with the inventive reactor or other reactor includes a first step of highly ionized sputter deposition of copper, which can optionally be used to remove the barrier layer at the bottom of the via, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and a third step of electroplating copper into the hole to complete the metallization. The first two steps can be also used with barrier metals.Type: ApplicationFiled: September 3, 2004Publication date: March 17, 2005Inventors: Praburam Gopalraja, Jianming Fu, Fusen Chen, Girish Dixit, Zheng Xu, Wei Wang, Ashok Sinha
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Publication number: 20050051424Abstract: A sputtering process and magnetron especially advantageous for low-pressure plasma sputtering or sustained self-sputtering, in which the magnetron has a reduced area but full target coverage. The magnetron includes an outer pole face surrounding an inner pole face with a gap therebetween. The outer pole of the magnetron of the invention is smaller than that of a circular magnetron similarly extending from the center to the periphery of the target and has a substantially larger total magnetic intensity. Thereby, sputtering at low pressure and high ionization fraction is enabled.Type: ApplicationFiled: September 13, 2004Publication date: March 10, 2005Inventors: Jianming Fu, Praburam Gopalraja, Fusen Chen, John Forster
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Publication number: 20050020080Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper.Type: ApplicationFiled: August 18, 2004Publication date: January 27, 2005Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen Chen, Barry Chin, Gene Kohara, Zheng Xu, Hong Zhang
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Publication number: 20050006222Abstract: A magnetron sputter reactor (410) and its method of use, in which SIP sputtering and ICP sputtering are promoted is disclosed. In another chamber (412) an array of auxiliary magnets positioned along sidewalls (414) of a magnetron sputter reactor on a side towards the wafer from the target is disclosed. The magnetron (436) preferably is a small one having a stronger outer pole (442) of a first polarity surrounding a weaker inner pole (440) of a second polarity all on a yoke (444) and rotates about the axis (438) of the chamber using rotation means (446, 448, 450). The auxiliary magnets (462) preferably have the first polarity to draw the unbalanced magnetic field (460) towards the wafer (424), which is on a pedestal (422) supplied with power (454). Argon (426) is supplied through a valve (428). The target (416) is supplied with power (434).Type: ApplicationFiled: November 14, 2002Publication date: January 13, 2005Inventors: Peijun Ding, Rong Tao, Zheng Xu, Daniel Lubben, Suraj Rengarajan, Michael Miller, Arvind Sundarrajan, Xianmin Tang, John Forster, Jianming Fu, Roderick Mosely, Fusen Chen, Praburam Gopalraja
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Publication number: 20040266175Abstract: In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects.Type: ApplicationFiled: July 20, 2004Publication date: December 30, 2004Applicant: Applied Materials, Inc.Inventors: Fusen Chen, Ling Chen, Walter Benjamin Glenn, Praburam Gopalraja, Jianming Fu
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Publication number: 20040222082Abstract: In conjunction with sputtering a metal, especially copper, into high aspect-ratio holes in a wafer, an oblique ion milling method in which argon ions or other particles having energies in the range of 200 to 1500 eV are directed to the wafer at between 10 and 35° to the wafer surface to sputter etch material sputter deposited preferentially on the upper corners of the holes. The milling may be performed in the sputter deposition chamber either simultaneously with the deposition or after it or performed afterwards in a separate milling reactor. A plurality of ion sources arranged around the chamber improve angular uniformity or arranged axially improve radial uniformity or vary the angle of incidence. An annular ion source about the chamber axis allows a plasma current loop. Anode layer ion sources and sources composed of copper are advantageous.Type: ApplicationFiled: May 5, 2003Publication date: November 11, 2004Applicant: APPLIED MATERIALS, INC.Inventors: Praburam Gopalraja, Xianmin Tang, Jianming Fu, Mark A. Perrin, Jean Yue (Phillip) Wang, Arvind Sundarrajan, Hong Zhang, Jick Yu, Umesh Kelkar, Zheng Xu, Fusen Chen
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Publication number: 20040209460Abstract: Embodiments of the present invention provide a process sequence and related hardware for filling a patterned feature on a substrate with a metal, such as copper. The sequence comprises first forming a reliable barrier layer in the patterned feature to prevent diffusion of the metal into the dielectric layer through which the patterned feature is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the barrier layer at the bottom of the patterned feature, depositing a second barrier layer, and then filling the patterned feature with a metal, such as copper.Type: ApplicationFiled: May 7, 2004Publication date: October 21, 2004Inventors: Ming Xi, Paul Frederick Smith, Ling Chen, Michael X. Yang, Mei Chang, Fusen Chen, Christophe Marcadal, Jenny C. Lin
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Patent number: 6797620Abstract: A method and apparatus is provided for filling apertures formed in a substrate surface by depositing materials that selectively inhibit or limit the formation or growth of subsequent layers used to fill an aperture. In one aspect, a method is provided for processing a substrate including providing a substrate having a field and apertures formed therein, wherein the apertures each have a bottom and sidewalls, depositing a seed layer on the bottom and sidewalls of the apertures, depositing a growth-inhibiting layer on at least one of the field of the substrate or an upper portion of the sidewalls of the apertures, and depositing a conductive layer on the growth-inhibiting layer and the seed layer. Deposition of the growth-inhibiting layer improves fill of the aperture from the bottom of the aperture up to the field of the substrate.Type: GrantFiled: April 16, 2002Date of Patent: September 28, 2004Assignee: Applied Materials, Inc.Inventors: John S. Lewis, Srinivas Gandikota, Sivakami Ramanathan, Girish Dixit, Robin Cheung, Fusen Chen
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Patent number: 6790323Abstract: A magnetron especially advantageous for low-pressure plasma sputtering or sustained self-sputtering having reduced area but full target coverage. The magnetron includes an outer pole face surrounding an inner pole face with a gap therebetween. The outer pole of the magnetron of the invention is smaller than that of a circular magnetron similarly extending from the center to the periphery of the target and has a substantially larger total magnetic intensity. Thereby, sputtering at low pressure and high ionization fraction is enabled.Type: GrantFiled: July 30, 2001Date of Patent: September 14, 2004Assignee: Applied Materials, Inc.Inventors: Jianming Fu, Praburam Gopalraja, Fusen Chen, John Foster
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Patent number: 6787006Abstract: A multi-step sputtering process in plasma sputter reactor having target and magnetron operable in two modes, for example, in a substrate sputter etch and a substrate sputter deposition. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process with the inventive reactor or other reactor includes a first step of highly ionized sputter deposition of copper, which can optionally be used to remove the barrier layer at the bottom of the via, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and a third step of electroplating copper into the hole to complete the metallization. The first two steps can be also used with barrier metals.Type: GrantFiled: July 16, 2002Date of Patent: September 7, 2004Assignee: Applied Materials, Inc.Inventors: Praburam Gopalraja, Jianming Fu, Fusen Chen, Girish Dixit, Zheng Xu, Wei Wang, Ashok K. Sinha