Abstract: An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap.

Abstract: An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap.

Abstract: A power field effect transistor has a laterally extending channel region which is not formed by double diffusion. The channel region may be formed in epitaxial silicon which is not doped after being grown. The drain electrode of the transistor is disposed on a bottom surface of the substrate upon which the transistor structure is formed. When the transistor is turned on, the channel region inverts thereby forming a conductive path from a source region, laterally through the inverted channel region, substantially vertically through a sinker region to the underlying substrate, through the substrate, and to the drain electrode.

Abstract: A power semiconductor device having internal circuits characterized by an electrical breakdown during one mode of operation is implemented with a protective circuit. The electrical breakdown is controllably induced to occur at the protective circuit thereby diverting any breakdown in the active circuits. In the preferred embodiment, the power device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which the protective circuit is deposited as an annular diffusion ring having a shallow portion and a deep portion. The deep portion is higher in doping concentration than the shallow portion and includes a radius of curvature larger than the shallow portion. The radius of curvature of the deep portion can be adjusted to induce breakdown at or above the rated value of the MOSFET. The predetermined doping concentration of the deep portion can abort the breakdown prematurely to occur at the deep region instead of at the active circuits.

Abstract: A n-channel MOSFET device is formed with a selective high energy boron implantation into the N region of the n- channel where a photoresist is employed to cover the central portion over the channel. Small n- regions are formed near the channel source interface. These small n- regions have the advantages of preventing punch through. The selective implant regions have the additional advantages that the JFET resistance is not increased as a result of forming a punch through prevention region near the source channel boundary. Also disclosed in this invention is a p-type DMOS where a novel boron implantation is applied to reduce the threshold voltage. The boron is selectively implanted into the n-type channel near the source, i.e., a threshold sensitive region. The threshold voltage is reduced without unduly lowering the drain to source breakdown voltage.

Abstract: Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve a low threshold voltage. The improved MOSFET device is formed in a semiconductor substrate with a drain region formed near a bottom surface of the substrate supporting a plurality of double-diffused vertical cells thereon wherein each of the vertical cells including a pn-junction having a body region surrounding a source region and each of the vertical cell further including a gate above the pn-junction. Each of the vertical cells further includes a source-dopant segregation reduction layer for reducing a surface segregation between the source region and an oxide layer underneath the gate whereby the body surface peak dopant concentration near an interface between the source region and the body region is reduced for reducing a threshold voltage of the MOSFET device.

Abstract: The cell density of a trenched DMOS transistor is increased by overcoming the problem of lateral diffusion of deep P+body regions. This problem is solved in three versions. In a first version, the deep P+body region is formed using a high energy implant into a single epitaxial layer. In a second version, a double epitaxial layer is used with a somewhat lower but still high energy deep P+body implant. In a third version, there is no deep P+body implant but only the double epitaxial layer is used. The cell density is improved to more than 12 million cells per square inch in each of the three versions.

Abstract: A new DMOS fabrication process is disclosed.

Abstract: A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

Abstract: A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is formed by e.g. implantation prior to epitaxial growth of the overlying drift region. By providing an optimized doping profile for the buried layer region, it is ensured that avalanche breakdown occurs at the buried layer region/body region. Thus drain-source on resistance is reduced because the JFET region present in prior art devices is eliminated, while device ruggedness and reliability are enhanced.

Abstract: A termination structure (located along a transistor perimeter or a die edge) for a trenched MOSFET or other semiconductor device prevents the undesirable surface channelling phenomena without the need for any additional masking steps to form a channel stop. This structure is especially applicable to P-channel MOSFETs. In the prior art a mask defines a doped channel stop. Instead here, a blanket ion implantation of P-type ions is performed after the active area masking process. Thus this doped channel stop termination is in effect masked during fabrication by the field oxide. In another version the channel stop termination is an additional trench formed in the termination region of the MOSFET. The trench is conventionally lined with oxide and filled with a conductive polysilicon field plate which extends to the edge of the die. In another version, the doped and trenched channel stops are used in combination. The channel stops are enhanced by provision of field plates overlying them on the die surface.

Abstract: A termination structure (located along a transistor perimeter or a die edge) for a trenched MOSFET or other semiconductor device prevents the undesirable surface channelling phenomena without the need for any additional masking steps to form a channel stop. This structure is especially applicable to P-channel MOSFETs. In the prior art a mask defines a doped channel stop. Instead here, a blanket ion implantation of P-type ions is performed after the active area masking process. Thus this doped channel stop termination is in effect masked during fabrication by the field oxide. In another version the channel stop termination is an additional trench formed in the termination region of the MOSFET. The trench is conventionally lined with oxide and filled with a conductive polysilicon field plate which extends to the edge of the die. In another version, the doped and trenched channel stops are used in combination. The channel stops are enhanced by provision of field plates overlying them on the die surface.

Abstract: A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically.

Abstract: A contact probe for semiconductor in-line process monitoring or device measurement is disclosed in this invention which uses gallium, indium or any low-melting and low-vapor pressure electrically conductive alloy as a contact probing material. The probe can be used to directly measure mobile ion density without requiring the formation of aluminum dots on the semiconductor wafers. The safety issues caused by high temperature operation are also eliminated. The time requirement for process-equipment qualification is significantly reduced because the preparation time for aluminum dot formation is now eliminated. In comparison to the mercury probes, since in this invention, the contact is formed at high temperature thus leading to better contacts between the probe and the wafer, which in turn resulting in higher measurement accuracy. Furthermore, the conventional pin slip problem during elevated temperature stress is eliminated by the use of the contact probe of this invention.

Abstract: A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

Abstract: To reduce susceptibility to punchthrough, the channel region of the P body region of a trench field effect transistor is formed in a layer of lightly doped epitaxial silicon. As a result, the channel region has less counterdoping from the background epitaxial silicon and has a greater net P type dopant concentration. Due to the higher net dopant concentration of the P body region, the depletion regions on either side of the P body region expand less far inward through the P body region at a given voltage, thereby rendering the transistor less susceptible to source-to-drain punchthrough. To maintain a low R.sub.DSon, the relatively high conductivity of an accumulation region formed along a sidewall of the trench of the transistor when the transistor is on is used to form a conductive path from the channel region to an underlying relatively highly conductive layer upon which the lightly doped epitaxial layer is formed.

Abstract: A DMOS field effect transistor having its gate electrode located in a trench includes a lightly doped epitaxial layer overlying the usual epitaxial layer. The trench penetrates only part way through the upper epitaxial layer which is more lightly doped than is the underlying lower epitaxial layer. The lightly doped upper epitaxial layer reduces the electric field at the bottom of the trench, thus protecting the gate oxide from breakdown during high voltage operation. Advantageously the upper portion of the lightly doped upper epitaxial layer has little adverse effect on the transistor's on resistance.

Abstract: A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002), typically of substantially uniform thickness, lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. In this case, the second polycrystalline segment extends over a scribe-line section of the termination area so as to be scribed during a scribing operation.

Abstract: The present invention detects defects near the gate/trench-surface interface of trench transistors. Defects near this interface which cause long term reliability problems generally also result in charges being trapped near the interface. In accordance with one embodiment of the present invention, a negative voltage is applied to the gate of the trench transistor with its drain grounded and its source floating. A leakage current flowing between the gate and drain is measured as a function of the voltage applied to the gate. A transistor whose gate-drain leakage current exceeds a predetermined value at a specified gate voltage is deemed to be defective. In another embodiment of the present invention, the gate-drain leakage current is measured as described above and monitored over time. Charge accumulated near the gate-drain interface due to defects in the interface results in the gate-drain leakage current taking a longer period of time to fall off to its steady state value.

Abstract: A low threshold voltage power DMOS transistor structure is disclosed having a lightly doped channel region formed in a shallow layer of relatively lightly doped epitaxial silicon. The light doping of the shallow epitaxial layer minimizes variations in threshold voltage and local variations in punch-through susceptibility due to nonuniformities in epitaxial doping concentration. A relatively heavily doped epitaxial layer is disposed underneath the shallow lightly doped epitaxial layer to reduce the drain to source resistance, R.sub.DS. Because the relatively heavily doped epitaxial layer is located below the channel region and not in the regions of the structure most susceptible to body region punch-through, providing the relatively highly doped epitaxial layer does not cause variations in threshold voltage and does not cause variations in the reverse bias voltage at which punch-through across the body region occurs.