Patents by Inventor Gamal Refai-Ahmed

Gamal Refai-Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10770364
    Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: September 8, 2020
    Assignee: XILINX, INC.
    Inventors: Hong Shi, Suresh Ramalingam, Siow Chek Tan, Gamal Refai-Ahmed
  • Patent number: 10741998
    Abstract: Provided is a laser system that includes a laser head having a laser holder configured to house a laser beam and a lens for reflecting the laser beam at a predetermined wavelength, and a thermal-mechanical adjustment device disposed on the laser head and configured to adjust a temperature and an alignment of the laser beam, to maintain the predetermined wavelength of the laser beam.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: August 11, 2020
    Assignee: General Electric Company
    Inventors: Sandip Maity, Ying Zhou, David Peter Robinson, Gamal Refai-Ahmed
  • Patent number: 10720377
    Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 21, 2020
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Ho Hyung Lee, Hui-Wen Lin, Henley Liu, Suresh Ramalingam
  • Publication number: 20200152546
    Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 14, 2020
    Applicant: Xilinx, Inc.
    Inventors: Gamal Refai-Ahmed, Ho Hyung Lee, Hui-Wen Lin, Henley Liu, Suresh Ramalingam
  • Patent number: 10629512
    Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 21, 2020
    Assignee: XILINX, INC.
    Inventors: Hong-Tsz Pan, Jonathan Chang, Nui Chong, Henley Liu, Gamal Refai-Ahmed, Suresh Ramalingam
  • Publication number: 20200105642
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam, Cheang-Whang Chang
  • Patent number: 10529645
    Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10527670
    Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Ivor G. Barber, Suresh Ramalingam, Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, David M. Mahoney, Mohsen H. Mardi
  • Publication number: 20200006186
    Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Xilinx, Inc.
    Inventors: Hong-Tsz Pan, Jonathan Chang, Nui Chong, Henley Liu, Gamal Refai-Ahmed, Suresh Ramalingam
  • Publication number: 20190318975
    Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 17, 2019
    Applicant: Xilinx, Inc.
    Inventors: Hong Shi, Suresh Ramalingam, Siow Chek Tan, Gamal Refai-Ahmed
  • Patent number: 10262920
    Abstract: Chip packages and electronic devices are provided that include a thermal capacitance element that improves the operation of IC dies at elevated temperatures. In one example, a chip package is provided that includes an integrated circuit (IC) die, a lid thermally connected to the IC die, and a thermal capacitance element thermally connected to the lid. The thermal capacitance element includes a container and a capacitance material sealingly disposed in the container. The capacitance material has a phase transition temperature that is between 80 and 100 percent of a maximum designed operating temperature in degrees Celsius of the IC die.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: April 16, 2019
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Brian D. Philofsky, Anthony Torza
  • Publication number: 20180358280
    Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 13, 2018
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10147664
    Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: December 4, 2018
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Daniel Elftmann, Brian D. Philofsky, Anthony Torza
  • Publication number: 20180308783
    Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Xilinx, Inc.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Daniel Elftmann, Brian D. Philofsky, Anthony Torza
  • Patent number: 10096502
    Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: October 9, 2018
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Mohsen H. Mardi, Tien-Yu Lee, Ivor G. Barber, Cheang-Whang Chang, Jaspreet Singh Gandhi
  • Publication number: 20180284187
    Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Applicant: Xilinx, Inc.
    Inventors: Gamal Refai-Ahmed, Ivor G. Barber, Suresh Ramalingam, Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, David M. Mahoney, Mohsen H. Mardi
  • Patent number: 10085363
    Abstract: A thermal management system that provides cooling to an electronic device is disclosed. The thermal management system includes a surface having a plurality of extended elements thermally coupled to the surface, a plurality of vibrator assemblies configured to generate a cooling flow across the surface, and a mounting structure disposed atop the plurality of extended elements of the surface to position the plurality of vibrator assemblies relative to the surface. The mounting structure is configured to orient each of the plurality of vibrator assemblies to the surface at an angel, such that the cooling flow generated by the plurality of vibrator assemblies impinges on the extended elements at an angle.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: September 25, 2018
    Assignee: General Electric Company
    Inventors: Gamal Refai-Ahmed, Hendrik Pieter Jacobus de Bock, Yogen Vishwas Utturkar, Matthew A. Ferguson, Bryan Patrick Whalen, Christian M. Giovanniello
  • Patent number: 10054575
    Abstract: There are provided methods and devices for sensing hydrogen gas. For example, there is provided a method that includes drawing a sample into a channel. The method includes passing the sample over a collection plate to remove an extraneous gas in the sample, thus yielding a purified sample. The method further includes passing the purified sample on a sensing plate and measuring a concentration of hydrogen in the purified sample using the sensing plate. The measuring can include heating the sensing plate and correlating a change in resistance of the sensing plate with a specified concentration of hydrogen. Furthermore, the method can include regenerating the collection plate following the measuring.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 21, 2018
    Assignee: General Electric Company
    Inventors: Gamal Refai-Ahmed, David Peter Robinson
  • Patent number: 10043730
    Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: August 7, 2018
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Tien-Yu Lee, Ferdinand F. Fernandez, Suresh Ramalingam, Ivor G. Barber, Inderjit Singh, Nael Zohni
  • Patent number: RE48015
    Abstract: An electronic packaging assembly having a semiconductor integrated circuit and a plurality of interconnect components is provided. The plurality of interconnect components is operatively coupled to the semiconductor integrated circuit. Further, one or more interconnect components include one or more support elements having a first surface and a second surface, and one or more spring elements having a first end and a second end, and wherein first ends of the one or more spring elements are coupled to the first surface or the second surface of a respective support element.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: May 26, 2020
    Assignee: General Electric Company
    Inventors: Gamal Refai-Ahmed, David Mulford Shaddock, Arun Virupaksha Gowda, John Anthony Vogel, Christian Michael Giovanniello