Patents by Inventor Gamal Refai-Ahmed
Gamal Refai-Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11476556Abstract: A heat exchanger and an antenna assembly having the same are described herein that enable a compact antenna design with good thermal management. In one example, a heat exchanger is provided that includes tube-shaped body. A main cooling volume is formed between the top and bottom surfaces proximate to the outside wall. The main cooling volume has an inlet formed through the top surface and an outlet formed through the bottom surface. A return volume is formed adjacent the inside diameter wall and is circumscribed by the main cooling volume. The return volume has an outlet formed through the top surface and an inlet formed through the bottom surface. One or more exterior fins are coupled to an exterior side of the outside wall. A plurality of fins extend into the main cooling volume. A plurality of inner fins extend into a passage from the inside diameter wall.Type: GrantFiled: November 23, 2020Date of Patent: October 18, 2022Assignee: XILINX, INC.Inventors: Mohsen H. Mardi, Gamal Refai-Ahmed, Suresh Ramalingam, Volker Aue
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Patent number: 11469212Abstract: A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.Type: GrantFiled: August 25, 2016Date of Patent: October 11, 2022Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Bryan Black, Michael Z. Su, Gamal Refai-Ahmed, Joe Siegel, Seth Prejean
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Patent number: 11373929Abstract: A cooling plate assembly and electronic device having the same are provided which utilize active and passive cooling devices for improved thermal management of one or more chip package assemblies included in the electronic device. In one example, a cooling plate assembly is provided that includes a cooling plate having a first surface and an opposing second surface, a first active cooling device coupled to the first surface of the cooling plate, and a first passive cooling device coupled to the second surface of the cooling plate.Type: GrantFiled: February 3, 2020Date of Patent: June 28, 2022Assignee: XILINX, INC.Inventors: Gamal Refai-Ahmed, Chi-Yi Chao, Suresh Ramalingam, Hoa Lap Do, Anthony Torza, Brian Philofsky, Arun Kumar Varadarajan Rajagopal
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Patent number: 11355412Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.Type: GrantFiled: September 28, 2018Date of Patent: June 7, 2022Assignee: XILINX, INC.Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam, Cheang-Whang Chang
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Patent number: 11330738Abstract: An electronic device is provided that balances the force applied to temperature control elements such that stress within components of the electronic device can be effectively managed. In one example, an electronic device is provided that includes a printed circuit board (PCB), a chip package, a thermal management system, a thermal spreader, and first and second biasing members. The chip package is mounted to the PCB. The thermal management system and spreader are disposed the opposite of the chip package relative to the PCB. The first biasing member is configured to control a first force sandwiching the chip package between the thermal spreader and the PCB. The second biasing member is configured to control a second force applied by the thermal management system against the thermal spreader. The first force can be adjusted separately from the second force so that total forces applied to the chip package and PCB may be effectively balanced.Type: GrantFiled: December 23, 2020Date of Patent: May 10, 2022Assignee: XILINX, INC.Inventors: Gamal Refai-Ahmed, Chi-Yi Chao, Huayan Wang, Suresh Ramalingam, Volker Aue
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Patent number: 11328976Abstract: Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single integral piece. The primary base is attached to the thermal carrier. The carrier base has an exterior surface that at least a portion of which defines a die contact region. The thermal carrier has an internal volume aligned with the die contact region. A fluid is disposed in the internal volume. The fins are attached to and extend from the one or more sidewalls of the thermal carrier.Type: GrantFiled: March 3, 2020Date of Patent: May 10, 2022Assignee: XILINX, INC.Inventors: Gamal Refai-Ahmed, Chi-Yi Chao, Suresh Ramalingam, Hoa Lap Do, Anthony Torza, Brian D. Philofsky
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Patent number: 11246211Abstract: Micro devices having enhanced through printed circuit board (PCB) heat transfer are provided. In one example, a micro device is provided that includes a PCB, a thermal management device, a chip package, a bracket, and a plurality of extra-package heat conductors. The chip package has a first side facing the thermal management device and a second side mounted to a first side of the PCB. The bracket is disposed on a second side of the PCB that faces away from the chip package. The plurality of extra-package heat conductors are disposed laterally outward of the chip package and provide at least a portion of a thermally conductive heat transfer path between the bracket and the thermal management device through the PCB.Type: GrantFiled: March 1, 2021Date of Patent: February 8, 2022Assignee: XILINX, INC.Inventors: Gamal Refai-Ahmed, Nagadeven Karunakaran, Hoa Do, Suresh Ramalingam
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Patent number: 11195780Abstract: A chip package assembly and method for fabricating the same are provided which incorporate phase change materials within the chip package assembly for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die stacked on the substrate, a dielectric filler layer, a cover and a phase change material. The phase change material is sealed within a recess formed between the first IC dies and the cover.Type: GrantFiled: March 24, 2020Date of Patent: December 7, 2021Assignee: XILINX, INC.Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Suresh Ramalingam
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Patent number: 11145566Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die.Type: GrantFiled: February 10, 2020Date of Patent: October 12, 2021Assignee: XILINX, INC.Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Jaspreet Singh Gandhi, Cheang-Whang Chang
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Publication number: 20210305127Abstract: Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Inventors: Gamal REFAI-AHMED, Suresh RAMALINGAM, Ken CHANG, Mayank RAJ, Chuan XIE, Yohan FRANS
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Publication number: 20210249328Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die.Type: ApplicationFiled: February 10, 2020Publication date: August 12, 2021Inventors: Gamal REFAI-AHMED, Suresh RAMALINGAM, Jaspreet Singh GANDHI, Cheang-Whang CHANG
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Publication number: 20210193620Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Jaspreet Singh Gandhi, Cheang-Whang Chang
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Patent number: 10770364Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.Type: GrantFiled: April 12, 2018Date of Patent: September 8, 2020Assignee: XILINX, INC.Inventors: Hong Shi, Suresh Ramalingam, Siow Chek Tan, Gamal Refai-Ahmed
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Patent number: 10741998Abstract: Provided is a laser system that includes a laser head having a laser holder configured to house a laser beam and a lens for reflecting the laser beam at a predetermined wavelength, and a thermal-mechanical adjustment device disposed on the laser head and configured to adjust a temperature and an alignment of the laser beam, to maintain the predetermined wavelength of the laser beam.Type: GrantFiled: January 14, 2016Date of Patent: August 11, 2020Assignee: General Electric CompanyInventors: Sandip Maity, Ying Zhou, David Peter Robinson, Gamal Refai-Ahmed
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Patent number: 10720377Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.Type: GrantFiled: November 9, 2018Date of Patent: July 21, 2020Assignee: XILINX, INC.Inventors: Gamal Refai-Ahmed, Ho Hyung Lee, Hui-Wen Lin, Henley Liu, Suresh Ramalingam
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Publication number: 20200152546Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.Type: ApplicationFiled: November 9, 2018Publication date: May 14, 2020Applicant: Xilinx, Inc.Inventors: Gamal Refai-Ahmed, Ho Hyung Lee, Hui-Wen Lin, Henley Liu, Suresh Ramalingam
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Patent number: 10629512Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.Type: GrantFiled: June 29, 2018Date of Patent: April 21, 2020Assignee: XILINX, INC.Inventors: Hong-Tsz Pan, Jonathan Chang, Nui Chong, Henley Liu, Gamal Refai-Ahmed, Suresh Ramalingam
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Publication number: 20200105642Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: Xilinx, Inc.Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam, Cheang-Whang Chang
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Patent number: 10527670Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.Type: GrantFiled: March 28, 2017Date of Patent: January 7, 2020Assignee: XILINX, INC.Inventors: Gamal Refai-Ahmed, Ivor G. Barber, Suresh Ramalingam, Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, David M. Mahoney, Mohsen H. Mardi
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Patent number: RE48015Abstract: An electronic packaging assembly having a semiconductor integrated circuit and a plurality of interconnect components is provided. The plurality of interconnect components is operatively coupled to the semiconductor integrated circuit. Further, one or more interconnect components include one or more support elements having a first surface and a second surface, and one or more spring elements having a first end and a second end, and wherein first ends of the one or more spring elements are coupled to the first surface or the second surface of a respective support element.Type: GrantFiled: February 1, 2018Date of Patent: May 26, 2020Assignee: General Electric CompanyInventors: Gamal Refai-Ahmed, David Mulford Shaddock, Arun Virupaksha Gowda, John Anthony Vogel, Christian Michael Giovanniello