Patents by Inventor Gang Duan
Gang Duan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250149455Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a polyimide or a dielectric material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on the surface, a second diameter at the surface of the glass layer, and the first diameter is equal to the second diameter plus 1 micron or minus 1 micron; and a dielectric layer on the material at the surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.Type: ApplicationFiled: November 7, 2023Publication date: May 8, 2025Applicant: Intel CorporationInventors: Nicholas Haehn, Jeremy Ecton, Brandon C. Marin, Srinivas V. Pietambaram, Gang Duan
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Publication number: 20250144857Abstract: Various aspects may provide a molding system. The molding system may include a molding unit which includes a first mold panel and a second mold panel. The first mold panel and the second mold panel may include a mold cavity which surrounds a semiconductor workpiece along a side surface of the semiconductor workpiece, with the first mold panel and the second mold panel engaged with the semiconductor workpiece. Various aspects may also provide a molding method which utilize the molding system.Type: ApplicationFiled: November 2, 2023Publication date: May 8, 2025Inventors: Zhixin XIE, Yi LI, Jesse JONES, Gang DUAN, Andrew JIMENEZ, Jung Kyu HAN, Yekan WANG
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Publication number: 20250125201Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first through-hole and a second through-hole, the first through-hole spaced apart from and smaller than the second through-hole; and a conductive material within the first through-hole, the conductive material to extend a full length of the first through-hole. The example apparatus further includes a dielectric material within the second through-hole, the dielectric material between an electronic component within the second through-hole and a sidewall of the second through-hole.Type: ApplicationFiled: December 17, 2024Publication date: April 17, 2025Applicant: Intel CorporationInventors: Brandon Christian Marin, Whitney Bryks, Gang Duan, Jeremy Ecton, Jason Gamba, Haifa Hariri, Sashi Shekhar Kandanur, Joseph Peoples, Srinivas Venkata Ramanuja Pietambaram, Mohammad Mamunur Rahman, Bohan Shan, Joshua James Stacey, Hiroki Tanaka, Jacob Ryan Vehonsky
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Publication number: 20250126814Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having a first hole and a second hole, the second hole larger than an electronic component disposed therein, a width of the electronic component larger than a width of the first hole. The example apparatus further includes a conductive material that substantially fills the first hole; and a dielectric material that substantially fills a space within the second hole surrounding the electronic component.Type: ApplicationFiled: December 17, 2024Publication date: April 17, 2025Applicant: Intel CorporationInventors: Brandon Christian Marin, Whitney Bryks, Gang Duan, Jeremy Ecton, Jason Gamba, Haifa Hariri, Sashi Shekhar Kandanur, Joseph Peoples, Srinivas Venkata Ramanuja Pietambaram, Mohammad Mamunur Rahman, Bohan Shan, Joshua James Stacey, Hiroki Tanaka, Jacob Ryan Vehonsky
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Publication number: 20250125202Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having an opening between opposing first and second surfaces of the glass layer; an electronic component within the opening; a dielectric material within the opening between the electronic component and a sidewall of the opening; and a through-glass via including a conductive material that extends through the glass layer.Type: ApplicationFiled: December 17, 2024Publication date: April 17, 2025Applicant: Intel CorporationInventors: Brandon Christian Marin, Whitney Bryks, Gang Duan, Jeremy Ecton, Jason Gamba, Haifa Hariri, Sashi Shekhar Kandanur, Joseph Peoples, Srinivas Venkata Ramanuja Pietambaram, Mohammad Mamunur Rahman, Bohan Shan, Joshua James Stacey, Hiroki Tanaka, Jacob Ryan Vehonsky
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Publication number: 20250125307Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.Type: ApplicationFiled: December 18, 2024Publication date: April 17, 2025Applicant: Intel CorporationInventors: Jeremy Ecton, Jason M. Gamba, Brandon C. Marin, Srinivas V. Pietambaram, Xiaoxuan Sun, Omkar G. Karhade, Xavier Francois Brun, Yonggang Li, Suddhasattwa Nad, Bohan Shan, Haobo Chen, Gang Duan
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Publication number: 20250120102Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first opening and a second opening spaced apart from the first opening, the second opening having a greater width than the first opening. The example apparatus further includes a conductive material adjacent a first wall of the first opening; and a dielectric material adjacent a second wall of the second opening.Type: ApplicationFiled: December 17, 2024Publication date: April 10, 2025Applicant: Intel CorporationInventors: Brandon Christian Marin, Whitney Bryks, Gang Duan, Jeremy Ecton, Jason Gamba, Haifa Hariri, Sashi Shekhar Kandanur, Joseph Peoples, Srinivas Venkata Ramanuja Pietambaram, Mohammad Mamunur Rahman, Bohan Shan, Joshua James Stacey, Hiroki Tanaka, Jacob Ryan Vehonsky
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Publication number: 20250112175Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Brandon C. Marin, Jesse C. Jones, Yosef Kornbluth, Mitchell Page, Soham Agarwal, Fanyi Zhu, Shuren Qu, Hanyu Song, Srinivas V. Pietambaram, Yonggang Li, Bai Nie, Nicholas Haehn, Astitva Tripathi, Mohamed R. Saber, Sheng Li, Pratyush Mishra, Benjamin T. Duong, Kari Hernandez, Praveen Sreeramagiri, Yi Li, Ibrahim El Khatib, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Gang Duan, Jeremy Ecton, Suddhasattwa Nad, Haobo Chen, Robin Shea McRee, Mohammad Mamunur Rahman
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Publication number: 20250112140Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a core with a first width, and the core comprises a glass layer. In an embodiment, a via is provided through a thickness of the core, where the via is electrically conductive. In an embodiment, a first layer is provided over the core, where the first layer comprises a second width that is smaller than the first width. In an embodiment, a second layer is provided under the core, where the second layer comprises a third width that is smaller than the first width.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Inventors: Rahul BHURE, Mitchell PAGE, Joseph PEOPLES, Jieying KONG, Nicholas S. HAEHN, Astitva TRIPATHI, Bainye Francoise ANGOUA, Yosef KORNBLUTH, Daniel ROSALES-YEOMANS, Joshua STACEY, Aaditya Anand CANDADAI, Yonggang Yong LI, Tchefor NDUKUM, Scott COATNEY, Gang DUAN, Jesse JONES, Srinivas Venkata Ramanuja PIETAMBARAM, Dilan SENEVIRATNE, Matthew ANDERSON
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Publication number: 20250112124Abstract: DEEP CAVITY ARRANGEMENTS ON INTEGRATED CIRCUIT PACKAGING An electronic package, comprises a substrate core; dielectric material of one or more dielectric material layers over the substrate core, and having a plurality of metallization layers comprising an upper-most metallization layer; and an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer. The package also has a metallization pattern within the dielectric material and below the IC die; and a gap within the dielectric material and extending around the metallization pattern.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Jeremy Ecton, Aleksandar Aleksov, Leonel Arana, Gang Duan, Benjamin Duong, Hongxia Feng, Tarek Ibrahim, Brandon C. Marin, Tchefor Ndukum, Bai Nie, Srinivas Pietambaram, Bohan Shan, Matthew Tingey
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Publication number: 20250112162Abstract: An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is located on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer. The lower dielectric material layer has an upper facing surface facing in a direction of the IC die adjacent the conductive feature that is vertically offset from the horizontal plane.Type: ApplicationFiled: September 30, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Zheng Kang, Tchefor Ndukum, Yosuke Kanaoka, Jeremy Ecton, Gang Duan, Jefferson Kaplan, Yonggang Yong Li, Minglu Liu, Brandon C. Marin, Bai Nie, Srinivas Pietambaram, Shriya Seshadri, Bohan Shan, Deniz Turan, Vishal Bhimrao Zade
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Publication number: 20250112136Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
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Publication number: 20250112164Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Onur OZKAN, Ryan CARRAZZONE, Rui ZHANG, Haobo CHEN, Ziyin LIN, Yiqun BAI, Kyle ARRINGTON, Jose WAIMIN, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Venkata Rajesh SARANAM, Shripad GOKHALE, Kartik SRINIVASAN, Edvin CETEGEN, Mine KAYA, Nicholas S. HAEHN, Deniz TURAN
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Publication number: 20250112100Abstract: An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to the first package conductive features. Third interconnects excluding solder couple the bridge with the second package conductive features. The bridge couples the first and second IC die with each other, and the first and second IC die with the second package conductive features. A pitch of conductive features in the first interconnects is less than a pitch of conductive features in the second interconnects.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Robert May, Hiroki Tanaka, Tarek Ibrahim, Lilia May, Jason Gamba, Benjamin Duong, Brandon Marin, Srinivas Pietambaram, Gang Duan, Suddhasattwa Nad, Jeremy Ecton
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Publication number: 20250112138Abstract: Microelectronic integrated circuit package structures include an apparatus having a substrate comprising a layer of glass, the substrate comprising one or more through glass vias (TGVs) extending through the layer of glass. Individual TGVs comprise a TGV sidewall, an organic dielectric layer on the TGV sidewall and a conductive layer on the organic dielectric layer.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Srinivas Pietambaram, Gang Duan, Sameer Paital, Zhixin Xie, Rahul Manepalli, Jieying Kong
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Publication number: 20250112085Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Bohan Shan, Ziyin Lin, Haobo Chen, Yiqun Bai, Kyle Arrington, Jose Waimin, Ryan Carrazzone, Hongxia Feng, Dingying Xu, Srinivas Pietambaram, Minglu Liu, Seyyed Yahya Mousavi, Xinyu Li, Gang Duan, Wei Li, Bin Mu, Mohit Gupta, Jeremy Ecton, Brandon C. Marin, Xiaoying Guo, Ashay Dani
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Publication number: 20250110289Abstract: A ferrule of an optical connector device is to accept one or more optical fibers in one or more fiber holes of the ferrule, the ferrule is formed from a dielectric material. The ferrule includes a face to interface with an optical socket of another device, where ends of the one or more optical fibers are exposed at the face to communicate photon signals with another device. The ferrule further includes alignment features formed in the dielectric layer to align the ends of the one or more optical fibers with one or more waveguides of the other device.Type: ApplicationFiled: September 30, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Benjamin T. Duong, Gang Duan, Sandeep Gaan, Donald Hammon, Wesley B. Morgan
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Publication number: 20250112161Abstract: Methods and apparatus to connect interconnect bridges to package substrates are disclosed. An example package substrate includes a dielectric layer including a cavity, a first contact pad positioned in the cavity, a first semiconductor die including a second contact pad and a third contact pad, the second contact pad positioned on a first surface of the first semiconductor die, the third contact pad positioned on a second surface of the first semiconductor die, the second surface opposite the first surface, the second contact pad coupled to the first contact pad, the third contact pad to be coupled to a second semiconductor die, and a non-conductive material surrounding the first contact pad and the second contact pad.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Minglu Liu, Seyyed Yahya Mousavi, Yingying Zhang, Gang Duan, Andrey Gunawan, Yosuke Kanaoka, Yiqun Bai, Ziyin Lin, Bohan Shan, Dingying Xu, Srinivas Pietambaram, Hong Seung Yeon
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Publication number: 20250112163Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Pratyush Mishra, Pratyasha Mohapatra, Srinivas Pietambaram, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Yosef Kornbluth, Kuang Liu, Astitva Tripathi, Yuqin Li, Rengarajan Shanmugam, Xing Sun, Brian Balch, Darko Grujicic, Jieying Kong, Nicholas Haehn, Jacob Vehonsky, Mitchell Page, Vincent Obiozo Eze, Daniel Wandera, Sameer Paital, Gang Duan
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Publication number: 20250112165Abstract: Anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. An example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Brandon Marin, Hiroki Tanaka, Robert May, Srinivas Pietambaram, Gang Duan, Suddhasattwa Nad, Numair Ahmed, Jeremy Ecton, Benjamin Taylor Duong, Bai Nie, Haobo Chen, Xiao Liu, Bohan Shan, Shruti Sharma, Mollie Stewart
