Patents by Inventor Gang Duan

Gang Duan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230146165
    Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 11, 2023
    Inventors: Srinivas PIETAMBARAM, Kristof DARMAWIKARTA, Gang DUAN, Yonggang LI, Sameer PAITAL
  • Patent number: 11646274
    Abstract: An integrated circuit package may be formed comprising a substrate that includes a mold material layer and a signal routing layer, wherein the mold material layer comprises at least one bridge and at least one foam structure embedded in a mold material. In one embodiment, the substrate may include the mold material of the mold material layer filling at least a portion of cells within the foam structure. In a further embodiment, at least two integrated circuit devices may be attached to the substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: May 9, 2023
    Assignee: Intel Corporation
    Inventors: Mufei Yu, Gang Duan, Edvin Cetegen, Baris Bicen, Rahul Manepalli
  • Publication number: 20230137877
    Abstract: No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 4, 2023
    Inventors: Bohan SHAN, Haobo CHEN, Omkar KARHADE, Malavarayan SANKARASUBRAMANIAN, Dingying XU, Gang DUAN, Bai NIE, Xiaoying GUO, Kristof DARMAWIKARTA, Hongxia FENG, Srinivas PIETAMBARAM, Jeremy D. ECTON
  • Patent number: 11622448
    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Brandon C. Marin, Tarek Ibrahim, Srinivas Pietambaram, Andrew J. Brown, Gang Duan, Jeremy Ecton, Sheng C. Li
  • Publication number: 20230101629
    Abstract: Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Bohan Shan, Dingying Xu, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Jung Kyu Han, Xiaoying Guo, Jeremy D. Ecton, Santosh Tripathi, Bai Nie, Haobo Chen, Kyle Jordan Arrington, Yue Deng, Wei Wei
  • Publication number: 20230085646
    Abstract: An electronic device comprises a mold layer that includes multiple integrated circuit (IC) dice having contact pads, a glass core patch embedded in encapsulating material that surrounds the top, bottom, and sides of the glass core patch, and a first redistribution layer arranged between the first mold layer and the glass core patch. The first redistribution layer includes electrically conductive interconnect that electrically connects one or more contact pads of the IC dice to the glass core patch.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Jeremy D Ecton, Leonel R. Arana, Brandon C. Marin, Srinivas Venkata Ramanuja Pietambaram, Gang Duan
  • Publication number: 20230092242
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a glass core within a substrate in a package, with one or more through glass vias (TGV) that are filled with a conductive material to electrically couple a first side of the glass core with a second side of the glass layer opposite the first side. A pad, also of conductive material, is electrically and physically coupled with a first and/or second end of the conductive material of the TGV. A layer of dielectric material is between at least a portion of the pad and the surface of the glass core between the pad and the glass core during manufacturing, handling, and/or operation to facilitate a reduction of stress cracks in the glass core. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 23, 2023
    Inventors: Srinivas V. PIETAMBARAM, Sameer PAITAL, Kristof DARMAWIKARTA, Hiroki TANAKA, Brandon C. MARIN, Jeremy D. ECTON, Gang DUAN
  • Publication number: 20230087838
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a protective coating for an edge of a glass layer, in particular a glass core within a substrate of a package, where the protective coating serves to protect the edge of the glass core and fill in cracks at the edges of the glass. This protective coating will decrease cracking during stresses applied to the glass layer during manufacturing or operation. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Rahul N. MANEPALLI, Srinivas V. PIETAMBARAM, Ravindra TANIKELLA, Sameer PAITAL, Gang DUAN
  • Publication number: 20230092903
    Abstract: Methods and apparatus to embed host dies in a substrate are disclosed An apparatus includes a first die having a first side and a second side opposite the first side. The first side includes a first contact to be electrically coupled with a second die. The second side includes a second contact. The apparatus further includes a substrate including a metal layer and a dielectric material on the metal layer. The first die is encapsulated within the dielectric material. The second contact of the first die is bonded to the metal layer independent of an adhesive.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 23, 2023
    Inventors: Sameer Paital, Gang Duan, Srinivas Pietambaram, Yosuke Kanaoka, Tchefor Ndukum
  • Publication number: 20230087810
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Jeremy D. ECTON, Kristof DARMAWIKARTA, Suddhasattwa NAD, Oscar OJEDA, Bai NIE, Brandon C. MARIN, Gang DUAN, Jacob VEHONSKY, Onur OZKAN, Nicholas S. HAEHN
  • Publication number: 20230090449
    Abstract: Methods, systems, apparatus, and articles of manufacture to produce nano-roughened integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a substrate, a semiconductor die, and a metal interconnect to electrically couple the semiconductor die to the substrate, the metal interconnect including a nano-roughened surface.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Suddhasattwa Nad, Gang Duan, Jeremy Ecton, Brandon Marin, Ravindranath Mahajan
  • Publication number: 20230088392
    Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a first via is through the core, where the first via directly contacts the core. In an embodiment, a second via is through the core, and a sleeve is around the second via. In an embodiment, the sleeve comprises a material with a thermal conductivity that is greater than a thermal conductivity of the second via.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 23, 2023
    Inventors: Srinivas V. PIETAMBARAM, Gang DUAN, Rahul N. MANEPALLI, Ravindra TANIKELLA, Sameer PAITAL
  • Publication number: 20230086180
    Abstract: A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Onur Ozkan, Edvin Cetegen, Steve Cho, Nicholas S. Haehn, Jacob Vehonsky, Gang Duan
  • Publication number: 20230089684
    Abstract: A substrate for an electronic device may include one or more layers. The substrate may include a cavity defined in the substrate. The cavity may be adapted to receive a semiconductor die. The substrate may include a fiducial mark positioned proximate the cavity. The fiducial mark may be exposed on a first surface of the substrate. The fiducial mark may include a first region including a dielectric filler material. The fiducial mark may include a second region including a conductive filler material. In an example, the second region surrounds the first region. In another example, the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Yosuke Kanaoka, Robin Mcree, Gang Duan, Gautam Medhi, Huang-Ta Chen
  • Publication number: 20230091379
    Abstract: Embodiments disclosed herein include electronic packages with first level interconnects that comprise a first layer. In an embodiment, the electronic package comprises a package substrate and a pad on the package substrate. In an embodiment, the pad comprises copper. In an embodiment, a first layer is over the pad. In an embodiment, the first layer comprises iron. In an embodiment, a solder is over the first layer, and a die is coupled to the package substrate by the solder.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Liang HE, Yeasir ARAFAT, Jung Kyu HAN, Ali LEHAF, Gang DUAN, Steve S. CHO, Yue DENG
  • Publication number: 20230086920
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for a dam structure on a substrate that is proximate to a die coupled with the substrate, where the dam decreases the risk of die shift during encapsulation material flow over the die during the manufacturing process. The dam structure may fully encircle the die. During encapsulation material flow, the dam structure creates a cavity that moderates the different flow rates of material that otherwise would exert different pressures the sides of the die and cause to die to shift its position on the substrate. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 23, 2023
    Inventors: Liang HE, Jisu JIANG, Jung Kyu HAN, Gang DUAN, Yosuke KANAOKA, Jason M. GAMBA, Bai NIE, Robert Alan MAY, Kimberly A. DEVINE, Mitchell ARMSTRONG, Yue DENG
  • Publication number: 20230078395
    Abstract: Disclosed herein are embedded heterogeneous architectures having minimized die shift and methods for manufacturing the same. The architectures may include a substrate, a bridge, and a material attached to the substrate. The substrate may include a first subset of vias and a second subset of vias. The bridge may be located in between the first subset and the second subset of vias. The material may include a first portion located proximate the first subset of vias, and a second portion located proximate the second subset of vias. The first and second portions may define a partial boundary of a cavity formed within the substrate and the bridge may be located within the cavity.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 16, 2023
    Inventors: Robin Mcree, Yosuke Kanaoka, Gang Duan, Jinhe Liu, Timothy A. Gosselin
  • Publication number: 20230078099
    Abstract: A substrate of a microelectronic assembly is provided, the substrate comprising conductive traces through an organic dielectric, and a coating comprising silicon and oxygen. The substrate is configured to couple with a component electrically and mechanically by at least one or more conductive via through the coating, the conductive via being electrically connected to the conductive traces, such that the coating is between the organic dielectric and the component when coupled. In some embodiments, the component includes another coating comprising silicon and oxygen, with conductive vias through the second coating. The conductive vias and the coating of the substrate are configured to bind with the conductive vias and the coating of the component respectively to form hybrid bonds.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Gang Duan, Srinivas V. Pietambaram, Brandon C. Marin, Bai Nie
  • Publication number: 20230084379
    Abstract: Disclosed herein are local bridge-last architectures for heterogeneous integration applications and methods for manufacturing the same. The local bridge-last architectures may include a substrate, a first die, a second die, and a material. The substrate may define a cavity. The first and second dies may be connected to the substrate. The material may be attached to the substrate. The material may include a first portion and a second portion. The first portion of the material may be located proximate the first bump and the second portion of the material may be located proximate the second bump.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 16, 2023
    Inventors: Gang Duan, Srinivas Venkata Ramanuja Pietambaram, Aleksandar Aleksov, Tarek Ibrahim
  • Publication number: 20230085411
    Abstract: A microelectronic assembly is disclosed, comprising: a substrate having a core made of glass; and a first integrated circuit (IC) die and a second IC die coupled to a first side of the substrate. The core comprises a cavity, a third IC die is located within the cavity, and the core further comprises one or more conductive through-glass via (TGV) that facilitates electrical coupling between the first side of the substrate and an opposing second side of the substrate. In some embodiments, the cavity is a blind cavity; in other embodiments, the cavity is a through-hole. In some embodiments, the third IC die merely provides lateral coupling between the first IC die and the second IC die; in other embodiments, the third IC die also provides electrical coupling between the first side and the second side of the substrate with through-silicon vias.
    Type: Application
    Filed: September 16, 2021
    Publication date: March 16, 2023
    Applicant: Intel Corporation
    Inventors: Sameer Paital, Yonggang Li, Kristof Kuwawi Darmawikarta, Gang Duan, Srinivas V. Pietambaram