Abstract: Embodiments of a semiconductor die comprise: a first bond-pad on a first surface to couple to a package substrate, a second bond-pad on a second surface, the second surface being opposite to the first surface, a hole through the semiconductor die, a conductive pillar within the hole separated from sidewalls of the hole by an air gap, the conductive pillar coupled to the first bond-pad and the second bond-pad, and pathways conductively coupling at least two integrated circuit (IC) dies proximate to the second surface.

Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

Abstract: Techniques and mechanisms for a micro-LED (or “uLED”) device to facilitate communication of an optical signal which is propagated via a transparent substrate structure. In an embodiment, one or more recess structures are formed in a side of a transparent substrate structure, such as a glass core of a package substrate. A uLED structure extends partially through the transparent substrate structure in a first recess structure, and is oriented to transmit or receive an optical signal via the transparent substrate. In another embodiment, the uLED structure is coupled to integrated circuitry which provides functionality to operate the uLED structure, at different times, in either one of an optical signal receiver mode or an optical signal transmitter mode.

Abstract: Methods and apparatus for edge protected glass cores are disclosed herein. An example package substrate includes a first glass layer including a first surface, a second surface opposite the first surface, and first lateral surfaces extending between the first and second surfaces, the first glass layer having a first via extending between the first surface and the second surface; and a dielectric material in contact with the first surface of the first glass layer and in contact with the first lateral surfaces of the first glass layer.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

Abstract: Hybrid cores including adhesive promotion layers and related methods are disclosed. An example substrate core for an integrated circuit disclosed herein includes a frame including interior edge, a glass panel including an exterior edge, and an adhesion promotion layer disposed between the interior edge and the exterior edge.

Abstract: Embodiments disclosed herein include hybrid cores for electronic packaging applications. In an embodiment, a package substrate comprises a plurality of glass layers and a plurality of dielectric layers. In an embodiment, the glass layers alternate with the dielectric layers. In an embodiment, a through-hole through the plurality of glass layers and the plurality of dielectric layers is provided. In an embodiment a conductive through-hole via is disposed in the through-hole.

Abstract: Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers including interconnect bridges are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a cavity defined therein; a second glass layer different from the first glass layer; and an interconnect bridge at least partially in the cavity. The interconnect bridge electrically couples a first semiconductor die to a second semiconductor die.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (PID) or an organic non-photoimageable dielectric (non-PID); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.

Abstract: Systems, apparatus, articles of manufacture, and methods for stacks of glass layers including thin film capacitors are disclosed. An example substrate includes a first glass layer, a dielectric layer on the first glass layer, a second glass layer, the first glass layer between the dielectric layer and the second glass layer, and a capacitor in the layer.

Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; and a magnetic material lining a first wall of a first opening in the first glass layer and lining a second wall of a second opening in the second glass layer.

Abstract: An intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. The intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. The intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.

Abstract: Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); and a second glass layer having a second CTE, the second CTE different from the first CTE.

Abstract: Glass cores including multiple layers and related methods are disclosed. An apparatus disclosed herein includes a printed circuit board and an integrated circuit package coupled to the printed circuit board, the integrated circuit package including a die and a glass core including a first layer having a first coefficient of thermal expansion and a second layer having a second coefficient of thermal expansion different than the first coefficient of thermal expansion.

Abstract: Systems, apparatus, articles of manufacture, and methods for stacks of glass layers including deep trench capacitors are disclosed. An example substrate for an integrated circuit package disclosed herein includes a first glass layer, a second glass layer coupled to the first glass layer, and a deep trench capacitor embedded in the first core.

Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example integrated circuit (IC) package includes: a package core including a first glass sheet and a second glass sheet distinct from the first glass sheet, the first glass sheet having a different coefficient of thermal expansion (CTE) from the second glass sheet; a first redistribution layer on a first side of the package core; a second redistribution layer on a second side of the package core, the second side opposite the first side; and an interconnect extending through the package core, the interconnect including a magnetic material.

Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; a conductive material extending through a first hole in the first glass layer and a second hole in the second glass layer; and a magnetic material between an inner wall of the first hole and the conductive material.

Abstract: Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example package substrate includes: a first glass layer including a first through glass via extending therethrough, the first glass layer having a first coefficient of thermal expansion (CTE); and a second glass layer including a second through glass via extending therethrough, the second glass layer having a second CTE different from the first CTE, the first through glass via electrically coupled to the second through glass via.

Abstract: Various embodiments disclosed relate to methods of making hybrid bonds for semiconductor assemblies, such as including substrate, semiconductor dies, and/or interconnects. The present disclosure includes a hybrid bond assembly having a via and a dielectric layer, each of the via and the dielectric layer bonding two or more components to each other.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a glass core layer having a first surface layer and a second surface layer; multiple channels within the glass core layer between the first surface and the second surface layer; and a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material, wherein a first surface of the RDL contacts the first surface of the glass core layer.