Abstract: Methods, systems, apparatus, and articles of manufacture to produce nano-roughened integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a substrate, a semiconductor die, and a metal interconnect to electrically couple the semiconductor die to the substrate, the metal interconnect including a nano-roughened surface.

Abstract: Embodiments disclosed herein include electronic packages with first level interconnects that comprise a first layer. In an embodiment, the electronic package comprises a package substrate and a pad on the package substrate. In an embodiment, the pad comprises copper. In an embodiment, a first layer is over the pad. In an embodiment, the first layer comprises iron. In an embodiment, a solder is over the first layer, and a die is coupled to the package substrate by the solder.

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a first via is through the core, where the first via directly contacts the core. In an embodiment, a second via is through the core, and a sleeve is around the second via. In an embodiment, the sleeve comprises a material with a thermal conductivity that is greater than a thermal conductivity of the second via.

Abstract: A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.

Abstract: A substrate for an electronic device may include one or more layers. The substrate may include a cavity defined in the substrate. The cavity may be adapted to receive a semiconductor die. The substrate may include a fiducial mark positioned proximate the cavity. The fiducial mark may be exposed on a first surface of the substrate. The fiducial mark may include a first region including a dielectric filler material. The fiducial mark may include a second region including a conductive filler material. In an example, the second region surrounds the first region. In another example, the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a glass core within a substrate in a package, with one or more through glass vias (TGV) that are filled with a conductive material to electrically couple a first side of the glass core with a second side of the glass layer opposite the first side. A pad, also of conductive material, is electrically and physically coupled with a first and/or second end of the conductive material of the TGV. A layer of dielectric material is between at least a portion of the pad and the surface of the glass core between the pad and the glass core during manufacturing, handling, and/or operation to facilitate a reduction of stress cracks in the glass core. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for a dam structure on a substrate that is proximate to a die coupled with the substrate, where the dam decreases the risk of die shift during encapsulation material flow over the die during the manufacturing process. The dam structure may fully encircle the die. During encapsulation material flow, the dam structure creates a cavity that moderates the different flow rates of material that otherwise would exert different pressures the sides of the die and cause to die to shift its position on the substrate. Other embodiments may be described and/or claimed.

Abstract: Methods and apparatus to embed host dies in a substrate are disclosed An apparatus includes a first die having a first side and a second side opposite the first side. The first side includes a first contact to be electrically coupled with a second die. The second side includes a second contact. The apparatus further includes a substrate including a metal layer and a dielectric material on the metal layer. The first die is encapsulated within the dielectric material. The second contact of the first die is bonded to the metal layer independent of an adhesive.

Abstract: Disclosed herein are embedded heterogeneous architectures having minimized die shift and methods for manufacturing the same. The architectures may include a substrate, a bridge, and a material attached to the substrate. The substrate may include a first subset of vias and a second subset of vias. The bridge may be located in between the first subset and the second subset of vias. The material may include a first portion located proximate the first subset of vias, and a second portion located proximate the second subset of vias. The first and second portions may define a partial boundary of a cavity formed within the substrate and the bridge may be located within the cavity.

Abstract: A microelectronic assembly is disclosed, comprising: a substrate having a core made of glass; and a first integrated circuit (IC) die and a second IC die coupled to a first side of the substrate. The core comprises a cavity, a third IC die is located within the cavity, and the core further comprises one or more conductive through-glass via (TGV) that facilitates electrical coupling between the first side of the substrate and an opposing second side of the substrate. In some embodiments, the cavity is a blind cavity; in other embodiments, the cavity is a through-hole. In some embodiments, the third IC die merely provides lateral coupling between the first IC die and the second IC die; in other embodiments, the third IC die also provides electrical coupling between the first side and the second side of the substrate with through-silicon vias.

Abstract: Disclosed herein are local bridge-last architectures for heterogeneous integration applications and methods for manufacturing the same. The local bridge-last architectures may include a substrate, a first die, a second die, and a material. The substrate may define a cavity. The first and second dies may be connected to the substrate. The material may be attached to the substrate. The material may include a first portion and a second portion. The first portion of the material may be located proximate the first bump and the second portion of the material may be located proximate the second bump.

Abstract: A substrate of a microelectronic assembly is provided, the substrate comprising conductive traces through an organic dielectric, and a coating comprising silicon and oxygen. The substrate is configured to couple with a component electrically and mechanically by at least one or more conductive via through the coating, the conductive via being electrically connected to the conductive traces, such that the coating is between the organic dielectric and the component when coupled. In some embodiments, the component includes another coating comprising silicon and oxygen, with conductive vias through the second coating. The conductive vias and the coating of the substrate are configured to bind with the conductive vias and the coating of the component respectively to form hybrid bonds.

Abstract: Embodiments include package substrates and methods of forming the package substrates. A package substrate includes a first conductive layer in a first dielectric, a second dielectric over the first dielectric, and a second conductive layer in the second dielectric, where the second conductive layer includes first and second traces. The package substrate also includes a third conductive layer over the second dielectric, and a high dielectric constant (Dk) and low DK regions in the first and second dielectrics, where the high Dk region surrounds the first traces, and where the low Dk region surrounds the second traces. The high Dk region may be between the first and third conductive layers. The low Dk region may be between the first and third conductive layers. The package substrate may include a dielectric region in the first and second dielectrics, where the dielectric region separates the high Dk and low Dk regions.

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

Abstract: The present invention is a water dispersible copolymer for scavenging formaldehyde, the copolymer being based on acrylic copolymer comprising one or more acetoacetyl functional groups and one or more hydrophilic groups chemically bonded to its molecular backbone, wherein the acrylic copolymer has a number average molecular weight of 2000-100,000 g/mol; and wherein the acrylic copolymer comprises between 10 wt % and 30 wt % of the acetoacetyl functional groups relative to the weight of the acrylic copolymer. The present invention also refers to an aqueous dispersion containing said water dispersible copolymer, as well as an article coated by a coating comprising the aqueous dispersion.

Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.

Abstract: The invention is directed to a crosslinkable flame-retardant coating composition comprising the following components: a) a dendritic polymer having hydroxyl groups, wherein the dendritic polymer has a hydroxyl number in the range of 80 to 800, b) a polyol having at least 3 hydroxyl groups, c) an ammonium polyphosphate compound, d) a base coat polymer selected from a polycarbamate resin or a polymer bearing carboxyl groups, and e) a crosslinker for crosslinking the base coat polymer selected from a compound having two or more aldehyde groups, acetals or hemiacetals of the aldehydes, or a polycarbodiimide. Such a cross-linkable flame-retardant coating composition improves the overall appearance of the cross-linked base coating on a substrate and also imparts improved flame-retardancy.

Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.