Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein.

Abstract: Integrated circuit (IC) packages are disclosed. In some embodiments, an IC package includes a glass substrate, a micro light emitting diode (LED), a semiconductor die, one or more through glass vias (TGVs) and a package substrate. The micro LED is positioned over the glass substrate. The TGVs are integrated into the glass substrate and connect the micro LED to the semiconductor die. The semiconductor die is connected to the package substrate to receive external signals when connected to a motherboard.

Abstract: Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Abstract: A threat level analyzer probes for one or more threats within an application container in a container system. Each threat is a vulnerability or a non-conformance with a benchmark setting. The threat level analyzer further probes for one or more threats within a host of the container service. The threat level analyzer generates a threat level assessment score based on results from the probing of the one or more threats of the application container and the one or more threats of the host, and generates a report for presentation in a user interface including the threat level assessment score and a list of threats discovered from the probe of the application container and the host. A report is transmitted by the threat level analyzer to a client device of a user for presentation in the user interface.

Abstract: Techniques for a glass core inductor are disclosed. In the illustrative embodiment, an integrated circuit component includes a glass substrate and a fully-integrated voltage regulator (FIVR). The FIVR includes a glass core inductor that is embedded in the glass substrate. Each inductor turn of the inductor includes two angled through-glass vias and a trace on top of the glass substrate connecting the angled through-glass vias, resulting in an inductor with a cross-section in the shape of a triangle or trapezoid. The inductor may have a relatively large inductance per unit area, requiring less space or allowing for a larger inductance.

Abstract: Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.

Abstract: A microelectronic structure, a semiconductor package including the structure, an IC device assembly including the structure, and a method of making the structure. The microelectronic structure includes: a first buildup layer and a second buildup layer including respective first and second electrically conductive structures; and a bridge layer including a glass material extending across a width thereof, the bridge layer between the first buildup layer and the second buildup layer and comprising: an interconnect bridge including third electrically conductive structures coupling a first set of the first electrically conductive structures to a second set of the first electrically conductive structures. Through glass vias (TGVs) extending from a top surface to a bottom surface of the bridge layer, the TGVs coupling a third set of the first electrically conductive structures to at least some of the second electrically conductive structures.

Abstract: A method for recognizing a reference point associated with a fiducial marker including the steps of: obtaining or receiving image data of the fiducial marker; determining the degree of which the image data of the fiducial marker is aligned with one or more reference images; of which if the degree of alignment is determined to be less than an acceptable threshold predicting a set of coordinates of the reference point associated with the fiducial marker; incorporating the set of coordinates with the image data to form a modified image data; and determining the degree of which the modified image data of the fiducial marker is aligned with one or more reference images.

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface, an opposing second surface, and lateral surfaces extending between the first and second surfaces; a conductive via coupled to the first surface of the conductive pad; a liner on the second surface and on the lateral surfaces of the conductive pad, wherein a material of the liner includes nickel, palladium, or gold; a microelectronic component having a conductive contact; and an interconnect electrically coupling the conductive contact of the microelectronic component and the liner on the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin.

Abstract: In one embodiment, an integrated circuit device includes a first layer having input/output (IO) hub circuitry to interconnect a plurality of integrated circuit dies, and a second layer having a plurality of integrated circuit dies electrically connected to the IO hub circuitry. The first layer may include glass, and the IO hub circuitry may be in a die embedded within the first layer. The integrated circuit dies may be electrically connected to the IO hub circuitry through an interposer.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate, where the first substrate comprises glass, and a second substrate over the first substrate, where the second substrate comprises glass. In an embodiment, electrically conductive routing is provided in the second substrate. In an embodiment, a first die is over the second substrate, and a second die is over the second substrate. In an embodiment, the electrically conductive routing electrically couples the first die to the second die.

Abstract: Embodiments of a microelectronic assembly comprise: a first layer comprising a plurality of first integrated circuit (IC) dies in an organic dielectric material, the first layer having a first side and a second side opposite to the first side; a second layer on the first side of the first layer, the second layer comprising a second IC die in the organic dielectric material, the second IC die conductively coupling a pair of first IC dies in the plurality of first IC dies of the first layer; and a package substrate coupled to the second side of the first layer. The second IC die is coupled to the pair of first IC dies by interconnects having a pitch less than 60 micrometers between adjacent interconnects, and the pair of first IC dies comprises TSVs conductively coupling circuits in the first IC dies with the interconnects.

Abstract: Embodiments disclosed herein include cores for package substrates. In an embodiment, the core comprises a first substrate, where the first substrate comprises glass. In an embodiment, the core further comprises a first through glass via (TGV) through the first substrate and a second substrate, where the second substrate comprises glass. In an embodiment, the core further comprises a second TGV through the second substrate, where the first TGV is aligned with the second TGV.

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate with a cavity, where the first substrate comprises glass. In an embodiment, a second substrate is in the cavity. In an embodiment, a bond film covers a bottom of the second substrate and extends up sidewalls of the second substrate.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer comprises glass, a second layer over the first layer, where the second layer comprises glass, and a third layer over the second layer, where the third layer comprises glass. In an embodiment, a pair of traces are in the second layer, and a first gap is below the pair of traces, where the first gap is in the first layer and the second layer. In an embodiment, a second gap is above the pair of traces, where the second gap is in the second layer and the third layer.