Abstract: A method can include generating equipment specifications for a facility project at a field site by simulating physical phenomena using one or more computational simulators; using the equipment specifications and a computational facility planner system, generating a work breakdown structure for the facility project, where the work breakdown structure represents activities to be performed to deliver a defined scope of the facility project within a defined time; rendering a graphical user interface to a display that includes graphical controls for dependencies of the activities and equipment characterized by the equipment specifications; responsive to input received via one or more of the graphical controls, automatically updating at least durations of the activities; and, based at least in part on the updating, generating an optimal scenario for the facility project.

Abstract: Techniques are described for reducing the number of angles needed in structured illumination imaging of biological samples through the use of patterned flowcells, where nanowells of the patterned flowcells are arranged in, e.g., a square array, or an asymmetrical array. Accordingly, the number of images needed to resolve details of the biological samples is reduced. Techniques are also described for combining structured illumination imaging with line scanning using the patterned flowcells.

Abstract: Systems and methods for processing alert communications are provided herein. Some exemplary methods may include processing alert communications on a mobile client computing device, where the mobile client computing device having a mobile survey management application. The method may also include executing instructions stored in memory to: capture at least a portion of an electronic mail alert communication provided to the mobile client computing device, the electronic mail alert communication being provided to the mobile client computing device by a survey management application of an application server, to establish an active issue within the mobile survey management application, and provide notification to the survey management application that the active issue has been resolved.

Abstract: Systems and methods for processing alert communications are provided herein. Some exemplary methods may include processing alert communications on a mobile client computing device, where the mobile client computing device having a mobile survey management application. The method may also include executing instructions stored in memory to: capture at least a portion of an electronic mail alert communication provided to the mobile client computing device, the electronic mail alert communication being provided to the mobile client computing device by a survey management application of an application server, to establish an active issue within the mobile survey management application, and provide notification to the survey management application that the active issue has been resolved.

Abstract: A method for operating a non-volatile memory device, which is applicable to an n-channel non-volatile memory device, wherein a positive voltage is applied to the control gate, a negative voltage is applied to the drain region while the source region is floating. Furthermore, a negative voltage is applied to the substrate to program to the n-channel memory device by the channel Fowler-Nordheim tunneling effect. To erase the n-channel non-volatile memory device, a negative voltage is applied to the control gate, a positive voltage is applied to the drain region, and the source region is floating. Moreover, a positive voltage is applied to the substrate to erase the n-channel memory device using the channel Fowler-Nordheim tunneling effect.

Abstract: A first compensation factor, a second compensation factor and a third compensation factor are provided to improve a capacitance-voltage (C-V) method for measuring an effective channel length of a metal-oxide-semiconductor field effect transistor (MOSFET), and an overlap length of a gate and a source and a drain of the transistor. The first compensation factor is calculated by measuring two unit length gate capacitances of the transistor. The second compensation factor is calculated by measuring two unit length overlap capacitances of the transistor. The third compensation factor is a ratio of the second compensation factor to the first compensation factor.

Abstract: A cantilever beam type micro-electromechanical system (MEMS) is formed on a substrate. Two first electrodes are formed in a first dielectric layer on the substrate and a waveguide line is formed between the first electrodes. A patterned sacrificial layer and an arm layer are formed on the substrate. Two second electrodes and a second dielectric layer are formed in the arm layer, and an optical grating is formed in the second dielectric layer. Finally, a cap layer is formed on the substrate, and the patterned sacrificial layer is removed.

Abstract: A method for operating a non-volatile memory device, which is applicable to an n-channel non-volatile memory device, wherein a positive voltage is applied to the control gate, a negative voltage is applied to the drain region while the source region is floating. Furthermore, a negative voltage is applied to the substrate to program to the n-channel memory device by the channel Fowler-Nordheim tunneling effect. To erase the n-channel non-volatile memory device, a negative voltage is applied to the control gate, a positive voltage is applied to the drain region, and the source region is floating. Moreover, a positive voltage is applied to the substrate to erase the n-channel memory device using the channel Fowler-Nordheim tunneling effect.

Abstract: A method for operating a non-volatile memory device, which is applicable to an n-channel non-volatile memory device, wherein a positive voltage is applied to the control gate, a negative voltage is applied to the drain region while the source region is floating. Furthermore, a negative voltage is applied to the substrate to program to the n-channel memory device by the channel Fowler-Nordheim tunneling effect. To erase the n-channel non-volatile memory device, a negative voltage is applied to the control gate, a positive voltage is applied to the drain region, and the source region is floating. Moreover, a positive voltage is applied to the substrate to erase the n-channel memory device using the channel Fowler-Nordheim tunneling effect.

Abstract: A transfer FET of a DRAM cell is formed having protective dielectric layers on the top and sides of the gate electrode. A first dielectric layer, preferably silicon dioxide, is provided over the transfer FET and a self-aligned etching process is used to etch through the first dielectric layer and to open a contact via to expose one of the source/drain regions of the transfer FET. A thick layer of polysilicon is deposited over the access circuitry and in contact with the exposed source/drain region of the transfer FET. A second dielectric layer is deposited over the surface of the thick layer of polysilicon and patterned to define a sacrificial structure on the polysilicon layer and over the one source/drain region. A third dielectric layer is deposited over the sacrificial structure and is anisotropically etched back to form sidewall spacer structures on the surface of the polysilicon layer.

Abstract: The present invention provides a C-V method for measuring an effective channel length in a device, which can simultaneously measure a gate-to-drain overlap length and a gate etch bias length in the device. In the present method, the measured length of the gate by using the present method has a deviation below 5% compared with the real gate length form SEM. Furthermore, the calculating method of the present invention only uses simple simultaneous equations, which can be measured by a man or a mechanism. As the layout rule shrunk, the present method provides a simple way to measure those parameters, which have become more and more important in the device.

Abstract: A method of forming shallow trench isolation (STI) uses a flowable insulating layer. In the method, a pad oxide layer is first formed on a substrate. A stop layer is formed on the pad oxide layer. Then, a trench is formed in the stop layer, the pad oxide layer and the substrate. A liner oxide layer is formed on the inner surface of the trench. Thereafter, a flowable insulating layer, such as a doped silicon oxide layer, is formed in the trench. An insulating layer, such as a silicon oxide layer, is formed on the flowable insulating layer. Finally, the stop layer and the pad oxide layer are removed so as to completely form shallow trench isolation.

Abstract: The present invention provides a C-V method for measuring an effective channel length in a device, which can simultaneously measure a gate-to-drain overlap length and a gate etch bias length in the device. In the present method, the measured length of the gate by using the present method has a deviation below 5% to compare with the real gate length form SEM. Furthermore, the calculating method of the present invention is only using simple simultaneous equations, which can be measured by a man or a mechanism. As the layout rule shrunk, the present method provides a simple way to measure those parameters, which become more and more important in the device.

Abstract: A method of manufacturing an inductor. A substrate is provided and then a plurality of linear-shaped first metallic layers is formed over the substrate. A first dielectric layer having a planar upper surface is over the substrate and the first metallic layers. A second metallic layer having a high magnetic conductance coefficient is embedded within the first metallic layer. A second dielectric layer is formed over the first dielectric layer and the second metallic layer. Via openings are formed in the first and the second dielectric layer directly above each end of each linear-shaped first metallic layer. Conductive material is deposited into the via openings to form plugs. A plurality of linear-shaped third metallic layers is formed so that the first metallic layer, the plug and the third metallic layer together form a spiral path. A dual damascene process may also be used to form the plugs and the third metallic layers.

Abstract: In present invention we provide a vertical two-transistor memory cell consisted of a MOS transistor and an ETOX cell. One of the drain or source of the MOS transistor is connected to the control gate of the ETOX cell, the other is acted as the control gate of the vertical two-transistor memory cell and is connected to a control line. And the gate of the MOS transistor is acted as the select gate of the vertical two-transistor memory cell and is connected to a word line. The drain of ETOX cell is connected to a bit line, and the source of ETOX cell is grounded. The vertical two-transistor memory cell can be programmed by channel Fowler-Nordheim tunneling of electrons which is injected from the substrate through the channel and tunnel oxide into the floating gate. Such memory cell can avoid the word line disturb by controlling the word line.

Abstract: A method of forming a self-aligned silicide layer. A planarization process is performed to form a gate with a planar top surface. Due to the planar top surface of the gate, the reactivity and the uniformity of thickness of the subsequently formed silicide layer on the top surface of the gate are improved, such that the resistance of the silicide is reduced, and the performance of the device is improved.

Abstract: A structure of self-aligned metal silicide. A gate oxide layer is formed on a substrate. A gate with a sidewall and a top surface thereof is formed on the gate oxide layer. A first silicidation step is performed to form a first metal silicide layer on both the sidewall and the top surface. A spacer is formed to cover the first metal silicide layer on the sidewall of the gate. An ion implantation is performed to form a source/drain region in the substrate with the gate as a mask. A second silicidation step is formed to form a second metal silicide layer on the source/drain region.

Abstract: A flash memory cell. A spacer is formed on a sidewall of a controlling gate. A self-aligned source/drain region can thus be formed by the formation of the spacer. The tunneling oxide layer is then formed on the source/drain region instead of on the controlling gate. Thus, the tunneling oxide layer is formed with a self-aligned process.

Abstract: Alternative methods are provided for fabricating a hybrid isolation structure on a semiconductor substrate, wherein, the hybrid isolation structure includes a shallow trench isolation (STI) and a field oxide isolation formed by local oxidation of silicon (LOCOS). In detail, the STI is formed within a device region that is operated at a low working voltage, a logic device region, to efficiently enhance the device density. On the other hand, the LOCOS isolation is formed within a device region that is operated at a high working voltage, a memory device region, to ensure the reliability and performance of the devices.

Abstract: A method of fabricating a flash memory is described. First, a shallow trench isolation structure is formed on the substrate, so that the surface of the shallow trench isolation structure is projected above the surface of the substrate. Then, a spacer is formed on the sidewall of the shallow trench isolation structure, which projects above the surface of the substrate. With the spacer serving as a mask, a gate oxide layer not covered by the spacer is etched to expose the substrate. By thermal oxidation, a self-aligned tunneling oxide layer is formed on the exposed substrate. The spacer is then removed. A floating gate is formed on the tunneling oxide layer. In addition, a dielectric layer and a control gate are formed on the floating gate in sequence, thus completing the flash memory structure.