Abstract: A method of fabricating a flash memory. After the formation of a trench isolation structure, openings are formed, in a direction perpendicular to the orientation of the trench isolation structure, in order to form a buried bit line. A spacer is formed on the opening sidewall of the bit line in which the distance between a top of the spacer and the interface of a substrate and a pad oxide layer is the depth of the source/drain region. The opening is then filled with a doped polysilicon conducting layer used as the buried bit line. The dopant from the polysilicon conducting layer is driven into the substrate to form the source/drain region.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor on a semiconductor substrate is described. The invention introduces an air chamber with a low dielectric constant between the gate and the source/drain region so as to lower the fringing electric field between the gate and the source/drain region. Moreover, the dielectric constant of the dielectric layer between the gate and the source/drain region is reduced. Therefore, the gate-to-drain capacitance is decreased in the MOS transistor.

Abstract: A method of fabricating a dynamic random access memory is disclosed, which mainly utilizing selective liquid-phase deposition process to form an insulation layer on the gate electrode structure.

Abstract: A DRAM cell includes a transfer FET on a substrate and includes a charge storage capacitor formed using a process that avoids high temperature processing steps and which emphasizes low cost processes. The transfer FET is covered with a conformal sacrificial layer of doped oxide, preferably phosphorus silicate glass. A contact opening is formed through the layer of doped oxide to expose one of the source/drain regions of the FET and a doped polysilicon layer is deposited over the layer of doped oxide and in contact with the source/drain region. The layer of conductor is patterned to define the lateral extent of at least a portion of the lower electrode and then the doped oxide layer is removed from between the gate electrode and the polysilicon layer in a wet etching process. Particularly when this wet etching process removes the preferred phosphorus silicate glass sacrificial layer, this process can be accomplished at high speed and with minimal process complexity.

Abstract: A method of fabricating the storage capacitor for the memory cell units of DRAM IC devices is disclosed. The method is not constrained by the resolution limitations commonly seen in traditional photolithography. Self-aligned anisotropic procedure can be employed to form contact opening having reduced dimension. The smaller via formed in the opening can effectively prevent the situation in which the via is short-circuited with other components of the cell unit. Device fabrication yield rate can thus be improved.

Abstract: A method of fabricating a capacitor. A transistor is formed on a substrate. The transistor comprises a gate and a source/drain region. A dielectric layer is formed over the substrate. A covering layer is formed on the dielectric layer. Portions of the covering layer and the dielectric layer are removed to form a contact opening. The contact opening exposes a portion of the source/drain region. A polysilicon layer is formed over the substrate to fill the contact opening. The polysilicon layer is electrically coupled with the source/drain region. A patterned photoresist layer is formed on the polysilicon layer above the contact opening. An anisotropic etching step is performed with the photoresist layer serving as a mask until a portion of the covering layer is exposed. An oxide layer is formed on the exposed covering layer. The surface of the oxide layer is higher than the surface of the polysilicon layer. The photoresist layer is removed to expose a portion of a sidewall of the polysilicon layer.

Abstract: A method of fabricating a flash memory cell. A spacer is formed on a sidewall of a controlling gate. A self-aligned source/drain region can thus be formed by the formation of the spacer. The tunneling oxide layer is then formed on the source/drain region instead of on the controlling gate. Thus, the tunneling oxide layer is formed with a self-aligned process.

Abstract: A method of fabricating a non-volatile flash memory device, wherein a gate structure is formed on a substrate. The method includes at least the following steps. The substrate is implanted with first ions to form a source region in the substrate. A tunneling oxide layer is formed on the substrate. A silicon nitride layer is formed on the substrate. The silicon nitride is etched back to form a silicon nitride spacer on the sides of the gate structure. The substrate is implanted with second ions to form a drain region in the substrate. An oxide layer is formed over the substrate and the gate structure. Then, a polysilicon layer is formed on the oxide layer. The gate structure is used as a selection gate, the silicon nitride spacer is used to store electrons, and the polysilicon layer is used as a controlling gate. The flash memory device can free memory cells by from the influences of over-erased effect.

Abstract: A method for forming ETOX cells (Intel Type Flash EPROM Cell) using a self-aligned source etching process comprising the steps of depositing a silicon nitride layer up to a thickness of 100 .ANG. to 700 .ANG., and then etching back the layer to form spacers. Thereafter, common source regions are defined using a photomask, and then the field oxide layer is etched using either a wet etching method or a dry etching method having a high selectivity ratio. The spacers are capable of protecting the oxide/nitride/oxide ONO layer against any damages during processing, thereby avoiding charge retention and reliability problems.

Abstract: A method for manufacturing DRAM capacitor that utilizes a self-aligned etching process for fabricating the lower electrode of a capacitor instead of a conventional photolithographic process whose processing accuracy is dependent upon the resolution of light source used. Using a polysilicon layer as a mask and a silicon nitride layer as an etching stop layer, the self-aligned etching process is carried out to form a rather narrow contact window in the insulating layer. By forming this narrow contact window, proper isolation between a word line and its neighboring conductive layer is ensured. Hence, device reliability is increased.

Abstract: A method for forming the lower electrode of a capacitor comprising the steps of forming a first dielectric layer, a silicon nitride layer and an oxide layer over a substrate. Then, a first conducting layer is formed in an opening making electrical contact with a specified region of the substrate. Next, a first hemispherical grained silicon layer and a second dielectric layer are formed over the first conductive layer. Thereafter, the second dielectric layer, the first hemispherical grained silicon layer and the first conductive layer are patterned. Subsequently, a second conductive layer and a second hemispherical grained silicon layer are formed over the whole substrate structure. Next, portions of the second hemispherical grained silicon layer and the second conductive layer lying above the oxide layer and the second dielectric layer are removed. Finally, the second dielectric layer is removed to expose the first hemispherical grained silicon layer.

Abstract: A process of fabricating self-aligned contacts for a semiconductor memory IC device. The substrate of the memory device has formed thereon gate structures of the memory cell units for the memory device. The gate structures are regularly spaced apart by first sidewall spacers formed on sidewalls of the gate structures. Source/drain regions of the memory cell units are formed in the device substrate in regions between consecutive gate structures. The process includes first forming an insulating layer over the surface of the substrate, followed by anisotropically etching back the insulating layer until a predetermined thickness over and normal to the top surface of the gate structure is obtained. A photoresist layer is formed over the surface of the insulating layer, with openings exposing contact regions for the memory cell units. Second sidewall spacers are then formed on the sidewalls of the gate structures and the source/drain regions are exposed, by etching into the insulating layer through the openings.

Abstract: A method of manufacturing a flash memory structure that also includes the process of forming a shallow trench isolation structure. The method comprises the steps of providing a semiconductor substrate, and then forming a shallow trench isolation structure within the substrate. Thereafter, etching is carried out to form a shallow trench within a portion of the shallow trench isolation structure. The shallow trench is formed where a common source terminal is subsequently formed. Next, metallic material is deposited into the trench to form a buried metallic layer. Then, a stacked gate is formed above the semiconductor substrate. Finally, ions are implanted into the substrate on each side of the stacked gate using the stacked gate itself as a mask to form a source region and a drain region. The source region and the buried metallic layer are connected together to form a common source region.

Abstract: A shallow trench isolation structure is formed by providing a pad layer and a silicon nitride polish stop layer on a surface of a P-type silicon substrate. The silicon nitride polish stop layer and the pad oxide layer are patterned to define openings corresponding to portions of the substrate that will be etched to form trenches. Trenches are defined in the P-type silicon substrate by anisotropic etching. A boron doped oxide or glass is deposited along the walls and floor of the trench. An undoped TEOS oxide is provided over the doped oxide or glass to complete filling of the trench. The device is subjected to a high temperature reflow process, causing the dielectric materials to flow, partially planarizing the device and causing the boron of the first layer to diffuse into the walls and floor of the trench. Chemical mechanical polishing removes excess portions of the dielectric layers.

Abstract: A method for forming a DRAM capacitor comprising the steps of first depositing conductive material over a dielectric layer and into a contact opening already formed in the dielectric layer, then patterning the conductive layer using a photoresist layer. Next, a portion of the photoresist layer is removed to expose a peripheral strip on the upper surface of the conductive layer. Then, a liquid-phase deposition method is used to deposit a silicon oxide layer over the conductive layer and the dielectric layer. Due to the selectivity of liquid-phase deposition method, none of the silicon oxide layer is deposited over the photoresist layer. Hence, after the removal of the photoresist layer, the silicon oxide layer can be used as a mask for patterning the conductive layer again. The patterned conductive layer then becomes the cylindrical-shaped storage electrode of a DRAM capacitor.

Abstract: A method of fabricating a bit line on a semiconductor substrate is provided. First, an oxide layer is formed and patterned on the substrate. An epitaxial layer is formed on the exposed substrate after patterning the oxide layer. A first spacer and a second spacer are sequentially formed on the sidewalls of a opening of the oxide layer. A trench is formed by partially removing the epitaxial layer and the substrate. A liner oxide layer is formed in the trench after removing the second spacer. A polysilicon layer as a conductive layer is formed in the trench after removing the first spacer. Then, a step of ion implantation and an annealing step are carried out. A buried bit line is formed after etching back the polysilicon layer.

Abstract: A method of forming a shallow trench isolation in a semiconductor substrate. A mask layer is formed to cover an active region of the substrate. A trench is formed within the exposed substrate. The trench is filled with an insulation layer. The dimension of the mask layer is shrunk. A thermal oxidation process is performed to form an oxide protrusion between the trench and the active region. The mask layer is removed.

Abstract: A method for manufacturing a flash memory. A substrate having a patterned pad oxide layer formed thereon and a patterned mask layer on the pad oxide layer is provided. A doped region is formed in the substrate exposed by the patterned mask layer and the pad oxide layer. A spacer is formed on the sidewall of the patterned mask layer and the pad oxide layer to cover a portion of the doped region. A trench is formed in the substrate exposed by the mask layer and the spacer. An insulating layer is formed to fill the trench, wherein the insulating layer leveled with a top surface of the patterned mask layer. The patterned mask layer and the spacer are removed to respectively expose the patterned oxide layer and the portion of the doped region. A self-aligned tunnel oxide layer is formed on the portion of the doped region. A patterned first conductive layer is formed over the substrate to expose portions of the patterned pad oxide layer above the substrate excluding the doped region.

Abstract: A structure of a flash memory is disclosed. The flash memory includes a common drain, a memory unit which has at least one memory cell, and a depletion mode selector transistor. The depletion mode selector transistor isolates the common drain and the memory unit. Two terminals the depletion mode selector transistor are coupled to the common drain and the memory unit, respectively.

Abstract: A method of fabricating a capacitor in a DRAM. A semiconductor substrate having a metal-oxide-semiconductor is provided. Using only one photolithography process, a bottom electrode is formed. By forming a dielectric layer over the substrate, and a poly-silicon layer on the dielectric layer, a capacitor is formed.