Abstract: A method for manufacturing an interconnect. A substrate having a first dielectric layer and a barrier layer formed thereon is provided. A plurality of conductive wires is formed on the barrier layer. A second dielectric layer is formed on the barrier layer exposed by the conductive wires, wherein the second dielectric layer has a surface level between the top surfaces and the bottom surfaces of the conductive wires. A spacer is formed on each portion of the sidewalls of the conductive wires exposed by the second dielectric layer, wherein there is a gap between two adjacent spacers. The second dielectric layer is removed. A third dielectric layer is formed on the conductive wires, the spacer, the sidewalls of the conductive wires and the portion of the barrier layer exposed by the conductive wires and fills the gap to form an air cavity between the conductive wires under the spacer.

Abstract: A mask ROM uses a bit line structure having a vertically graded dopant distribution or a distinct two level dopant distribution. A bit line might include a highly doped region buried deeply within the substrate that is connected to a comparatively lightly doped region formed above the more highly doped region. The vertical structure of the bit line allows the bit line to be less resistive than the simpler shallow bit line structure conventionally used. The vertical structure (i.e., the two level or graded structure) of the bit line allows the bit line to have a lower doping immediately adjacent the channel region, which reduces the likelihood of punchthrough. The deeper, highly doped portions of the bit line are narrow and laterally confined so that well defined antipunchthrough implantations can be formed which lie between but separated from the more highly doped portions of the bit lines.

Abstract: A method for manufacturing shallow trench isolation structure in a substrate, in which by forming a doped region at the upper corners of a trench, the degree of oxidation in that region increases when the liner layer is formed over the exposed surface of the trench. Therefore, thickness of the liner layer at the upper corner regions of the trench is almost the same as in other regions. Consequently, a kink effect is prevented when a gate is subsequently formed over the active region of the substrate.

Abstract: A split-gate source side injection flash memory structure that utilizes the polysilicon spacers formed on the sidewalls of the control gate and the floating gate, and the difference in concentration and depth between the source region and the drain region. By applying suitable operating voltage to the polysilicon spacers above the respective source region and drain region, operation of the flash memory can be properly controlled. Because a source-side injection is obtained in this invention, hence a higher programming efficiency is achieved.

Abstract: A semiconductor fabrication method for fabricating a flash EEPROM (electrically erasable and programmable read-only memory) device uses STI (shallow-trench isolation) technique to form the field oxide isolation layers so as to make the EEPROM device suitable for fabrication at the submicron level of integration. By this method, the first step is to prepare a semiconductor substrate. Next, a plurality of field oxide isolation layers are formed through the STI technique to define active region in the substrate. After this, at least one gate structure is formed within the active region, which includes a tunnel oxide layer, a first conductive layer serving as a floating gate, a dielectric layer, a second conductive layer serving as a control gate, and a topping layer. Subsequently, an ion-implantation process is performed to form source/drain regions beside the gate structure. A sidewall spacer is then formed on the sidewall of the gate structure.

Abstract: The structure of a buried bit line. A substrate is provided and a trench is, formed within the substrate. Next, a trench insulating layer is located on a portion of the trench surface to expose a top corner of the trench. Then, a first conductive layer is fills the trench and forms a surface. Afterwards, a second conductive layer is formed on the surface and fills the trench, wherein the second conductive layer makes contact with the top corner, and a shallow junction region is located at the top corner and makes contact with the second conductive layer.

Abstract: A method of fabricating a split gate flash memory. A substrate is provided for implantation with first ions to form a source region in the substrate. Second ions are implanted into the substrate to form a drain region in the substrate, wherein the source region is connected to the drain region. A part of the substrate is defined to form a number of trenches, wherein the trenches are located between the source region and the drain region. A tunneling oxide layer is formed along the profile of the trenches and on the surface of the substrate. The trenches are subsequently filled with a first polysilicon layer, wherein the depth of the first polysilicon layer is between that of the source region and that of the drain region in the substrate. An inter-dielectric layer is formed over the surface on the substrate and the first polysilicon layer, and a second polysilicon layer is formed on the substrate.

Abstract: A method for forming a shallow trench isolation structure in a substrate includes the steps of forming a doped region around the future top corner regions of a trench. The concentration of dopants inside the doped region increases towards the substrate surface. Thereafter, a trench is formed in the substrate, and then a thermal oxidation operation is carried out. Utilizing the higher oxidizing rate for doped substrate relative to an undoped region, the upper corners of the trench become rounded corners. Subsequently, a liner oxide layer is formed over the substrate surface inside the trench using conventional methods. Finally, insulating material is deposited into the trench to form a trench isolation structure.

Abstract: A process of fabricating a mask type ROM is described wherein second type impurity ions are implanted into a semiconductor substrate having a first opposite type background impurity to form a depletion region adjacent the surface. A plurality of parallel nitride lines are formed on the surface, and a first gate oxide formed on the spaces between the nitride lines. Subsequently, a first layer of doped polycrystalline silicon is deposited over the nitride lines, and the layer etched back to expose the top surfaces of the nitride lines. After the nitride lines are removed, a thin gate oxide layer is formed on the exposed surface of the substrate, and on the surfaces of the resultant first polycrystalline gate electrode lines. A second layer of doped polycrystalline silicon is deposited over the polycrystalline silicon lines, and it is etched back. The etch back of the first, and also the second polycrystalline silicon layers, produces an elongated central depression in each of the resultant lines.

Abstract: A method of fabricating a flash memory. A heavily doped region with the opposite polarity of the drain region is formed between the channel region and the drain region. The heavily doped region is in a bar shape extending towards both the drain and the source regions along a side of the floating gate. Furthermore, the reading operation is performed in reverse by applying a zero voltage to the drain region, and a non-zero voltage to the source region.

Abstract: A DRAM capacitor is formed using a process that avoids high temperature processing steps and which emphasizes low cost processes. An interlayer dielectric, typically CVD TEOS oxide, is provided over the transfer FET and bit line contact of the DRAM cell. The interlayer dielectric is planarized and an etch stop layer is provided over the planarized surface of the etch stop layer. A contact via is formed to expose a source/drain region for the transfer FET. Doped polysilicon is provided to fill the contact via and to form a first layer of doped polysilicon over the etch stop layer. The first polysilicon layer is patterned to form a plate aligned over the contact via using a first photoresist mask and etching. The first photoresist mask is left in place over the plate and a first layer of selective oxide is deposited over the etch stop layer so that the first selective oxide layer does not deposit over the photoresist mask.

Abstract: A method is provided for fabricating an EEPROM (EEPROM (electrically erasable and programmable read-only memory) device, which can help improve the quality of the tunneling oxide layer in the EEPROM device for reliable operation of the EEPROM device. This method is characterized in that the portion of the tungsten silicide (WSi) layer that is directly laid above the tunneling oxide layer is removed, while still allowing all the other part of the tungsten silicide layer to remain unaltered. As a result, in the subsequent heat-treatment process, the degradation in the quality of the tunneling oxide layer that occurs in the prior art due to the forming of a trapping center therein can be prevented. The tunneling oxide layer is thus more assured in quality, allowing the resultant EEPROM to operate reliably with high performance.

Abstract: A method for forming a flash memory cell structure comprising the steps of providing a semiconductor substrate, and then sequentially forming a bottom conductive layer and a cap oxide layer over the substrate. Next, a pattern is defined in the conductive layer and the cap oxide layer. Subsequently, a thermal oxidation method is used to form a silicon oxide layer on the sidewalls of the bottom conductive layer. Then, a gate oxide layer is formed between the bottom conductive layers above the substrate. Thereafter, source/drain regions are formed in the semiconductor substrate. Then, spacer structures are formed adjacent to the silicon oxide layers. Using the spacer structures as masks, a portion of the gate oxide layer is etched. Then, the spacer structures are removed to expose the gate oxide layer. Next, a thermal oxidation method is used to form a tunneling oxide layer in the narrow region between the gate oxide layer. The tunneling oxide layer has a long narrow top profile.

Abstract: A method of fabricating a flash memory having a vertical floating gate terminal layer and controlling gate terminal layer structure, which is suitable for use in ultra-high density IC circuits, and which has two separate tunneling layers, one used for data programming and the other used for data erasure. The fabrication method includes a number of steps. A protruding plateau is first formed on the surface of a silicon substrate. Then, ions are implanted to form a drain region on the top surface of the protruding plateau, as well as to form source regions in the substrate on each side of and adjacent to the base of the protruding plateau. A gate oxide layer is formed on each side wall of the protruding plateau; exposing only part of the side wall of the drain region. A tunnel oxide layer that is thinner than the gate oxide layer, is formed above the surface of the silicon substrate so as to cover the source regions and drain region.

Abstract: A method for forming an isolation region in an integrated circuit is disclosed. The method includes forming a pad layer on a semiconductor substrate, and forming an oxidation masking layer on the pad layer, wherein the pad layer relieves stress from the oxidation masking layer. Next, portions of the oxidation masking layer and the pad layer are patterned and etched. A first oxide layer is thermally grown on the substrate, and a second oxide spacer is formed on a sidewall of the pad layer and the oxidation masking layer. After forming a nitride spacer on a surface of the second oxide spacer, the substrate is thermally oxidized to form the isolation region in the substrate.

Abstract: A DRAM is formed using a process which uses few critical lithography steps and which provides capacitor electrodes and bit line contacts in a self-aligned manner in a common set of processing steps. A multilayer stack including a gate oxide layer, a gate electrode layer, an etch stop layer, and a thicker sacrificial layer are provided over the active device regions of a semiconductor substrate. Photolithography and etching define gate electrodes and wiring lines with patterned etch stop layers and patterned sacrificial layers over and self-aligned with the gate electrodes and wiring lines. Source/drain regions are formed self aligned to the patterned stacks and then an insulating spacer is provided alongside the edges of the gate electrodes. A relatively thin, conformal polysilicon layer is provided over the patterned stacks and in contact with the source/drain regions adjacent the gate electrodes.

Abstract: A method of fabricating an electrostatic protection device, comprises a semiconductor substrate which includes a first type well, a second type well, and a field oxide layer in between. A first gate, a first spacer, and a first source/drain are formed in the first type well. The second type has a second gate, a second spacer, and the second source/drain formed therein. In addition, an oxide layer is distributed on the first gate, the second gate, a part of the first source/drain, and a part of the second source/drain. A silicide layer is formed on the uncovered first source/drain and the uncovered second source/drain. Therefore, the silicide layer and the gate oxide layer are spaced apart.

Abstract: A floating gate transistor is formed on an active device region defined between field isolation structures. A first polysilicon layer, or a layer of another conductor which can be used in diffusing impurities into the underlying silicon substrate, is provided on the active device region of the substrate and is covered by a layer of insulating material such as silicon oxide. The first polysilicon layer is doped by implantation of impurities, but no annealing step is performed at this time. An opening is formed through the polysilicon layer to expose the surface of the active device region. Oxide spacers and then nitride spacers are formed on the sidewalls of the opening in the first polysilicon layer to define a narrower opening.

Abstract: A method for manufacturing DRAM capacitor that utilizes a self-aligned operation to form a forked-shaped capacitor structure having dual trenches or a multiple of trenches. No additional masking steps are required, and the uneven surface produced by the method of this invention is able to increase the surface area of the lower electrode. Hence, a high capacitance for the DRAM capacitor is obtained and a high level integration of DRAM cells can be realized.

Abstract: A method for forming DRAM capacitor that utilizes the formation of an oxide layer and the subsequent etch-removal of a portion of the oxide layer located in the gap between a first masking layer and a second masking layer in order to form the minimum separation required between the lower electrodes of adjacent capacitors. Furthermore, when the etching operation is carried on into the conductive layer that lies below the oxide layer, the lower electrode of the capacitor is also patterned out. The manufacturing process in this invention does not use the conventional photolithographic technique, and therefore will not be limited by the resolution of the light source. Consequently, distance between two neighboring capacitors can be reduced, and a higher capacitance for the capacitors can be obtained.