Abstract: A pixel structure comprising: a diode body comprising: a base portion protruding from a substrate and a main portion on top of the base portion, wherein a footprint of the base portion is smaller than a footprint of the main portion, and wherein the main portion comprises first and second oppositely doped regions formed in a top portion of the main portion, wherein the first and second doped regions are formed in a central part and along a periphery, respectively, of the footprint of the main portion; a gate arranged to circumferentially surround the diode body, comprising a first gate portion surrounding the main portion and a second gate portion protruding inwardly from the first gate portion to undercut the main portion and surround the base portion; a gate dielectric layer arranged to separate the gate and the diode body; and first and second diode terminals, and a gate terminal.

Abstract: An example includes a method for producing a multipixel detector, the method including: providing a bottom layer including a first and a second bottom electrode, depositing an electrically insulating layer on the bottom layer, forming a first opening through the electrically insulating layer, depositing a first photon absorbing material in the first opening, forming a second opening through the electrically insulating layer, depositing a second photon absorbing material in the second opening, planarizing the deposited electrically insulating layer, the first photon absorbing material, and the second photon absorbing material to form a flat surface, and forming a common top electrode on top of the flat surface.

Abstract: A light sensor for spectrally resolved light detection, said light sensor comprises: an upper reflective element; a lower reflective element; a photo-sensitive element therebetween; a spacer element, configured to form the lower reflective element or arranged between the upper and the lower reflective element; wherein the elements form a stack of layers which define a resonance structure between the upper and the lower reflective element for providing a resonance of light; wherein the spacer element comprises at least two different materials, a distribution of which is different between different pixels in an array of pixels such that a resonance wavelength is different for different pixels; and wherein for a plurality of pixels, geometrical structures smaller than the resonance wavelength are defined by the at least two different materials.

Abstract: According to a preferred embodiment of the method of the invention, an assembly is produced comprising a temporary wafer and one or more tiles that are removably attached to the temporary wafer, preferably through a temporary adhesive layer. The tiles comprise a carrier portion and an active material portion. The active material portion is attached to the temporary carrier. The assembly further comprises a single continuous layer of the first material surrounding each of the one or more tiles. Then the back side of the carrier portions of the tiles and of the continuous layer of the first material are simultaneously planarized, and the planarized back sides of the tiles and of the continuous layer of the first material are bonded to a permanent carrier wafer, after which the temporary carrier wafer is removed.

Abstract: A back-end-of-line (BEOL) component includes a substrate and a first layer of dielectric material arranged on the substrate. The first layer of dielectric material includes openings. The BEOL component further includes a first layer of metal material arranged in the openings. The BEOL component further includes an etch stop layer arranged on top of the first layer of dielectric material. The BEOL component further includes a second layer of metal material in direct contact with the first layer of metal material. The second layer of metal material includes at least one projection extending above the etch stop layer. The BEOL component further includes a second layer of dielectric material arranged on top of the etch stop layer and surrounding the at least one projection.

Abstract: Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip has a substrate having a major surface. The semiconductor chip has a boundary defined on the major surface in accordance with a ground rule associated with a gate cut passing (CT) fin formed on the major surface. The semiconductor chip has multiple non-planar devices fabricated on the surface at the boundary. The CT fin forms a random distribution of field effect transistors (FETs) with varying work function metal (WFM) thickness that includes some FETs that fail the ground rule and other FETs that meet the ground rule. A physical unclonable function (PUF) region is defined in accordance with the random distribution.

Abstract: The embodiments herein describe authenticating a photomask used to fabricate an IC or a wafer. Because the IC may have been fabricated at a third-party IC manufacturer, the customer may want to ensure the manufacturer did not mistakenly use an incorrect mask, or that the mask was not altered or replaced with a rogue mask by a nefarious actor. That is, the embodiments herein can be used to identify when an IC manufacture (whether trusted or not) mistakenly used the wrong photomask, or to verify that a third-party IC manufacturer did not tamper with or replace the authentic photomask with a rogue mask. Advantageously, the embodiments herein can create a secure IC fabrication process to catch mistakes as well as ensure that non-trusted third-parties did not introduce defects into the IC.

Abstract: According to an aspect of the present inventive concept there is provided a microfluidic device comprising: at least one structure arranged in a pocket-defining layer defining a pocket in the pocket-defining layer; a semiconductor chip arranged in the pocket, the semiconductor chip comprising at least one electrode at the surface of the semiconductor chip; an electrical connection layer arranged above the semiconductor chip, wherein the electrical connection layer comprises electronic connections electrically connected to the at least one electrode and arranged to extend laterally in the electrical connection layer away from the semiconductor chip; at least one fluidic channel extending through the pocket-defining layer and above the semiconductor chip, the fluidic channel being arranged to be in fluidic communication with the at least one electrode.

Abstract: A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.

Abstract: A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.

Abstract: A light sensor for spectrally resolved light detection, said light sensor comprises: an upper reflective element; a lower reflective element; a photo-sensitive element therebetween; a spacer element, configured to form the lower reflective element or arranged between the upper and the lower reflective element; wherein the elements form a stack of layers which define a resonance structure between the upper and the lower reflective element for providing a resonance of light; wherein the spacer element comprises at least two different materials, a distribution of which is different between different pixels in an array of pixels such that a resonance wavelength is different for different pixels; and wherein for a plurality of pixels, geometrical structures smaller than the resonance wavelength are defined by the at least two different materials.

Abstract: An example includes a method for producing a multipixel detector, the method including: providing a bottom layer including a first and a second bottom electrode, depositing an electrically insulating layer on the bottom layer, forming a first opening through the electrically insulating layer, depositing a first photon absorbing material in the first opening, forming a second opening through the electrically insulating layer, depositing a second photon absorbing material in the second opening, planarizing the deposited electrically insulating layer, the first photon absorbing material, and the second photon absorbing material to form a flat surface, and forming a common top electrode on top of the flat surface.

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate elevator analytics and/or elevator optimization components are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a prediction component that can predict a current destination of an elevator passenger based on historical elevator usage data of the elevator passenger. The computer executable components can further comprise an assignment component that can assign the elevator passenger to an elevator based on the current destination.

Abstract: A computer-implemented method of ensuring integrity of an integrated circuit (IC) is provided. The computer-implemented method includes providing a design layer that meets design rule checks (DRCs), identifying a first critical dimension (CD) distribution of the design layer and using retargeting shapes in the design layer to enable a biasing of CDs of targets to enable a provision of two different CD distributions, which are DRC clean and which are separate from one another and which cannot be expressed by a single Gaussian distribution.

Abstract: According to a preferred embodiment of the method of the invention, an assembly is produced comprising a temporary wafer and one or more tiles that are removably attached to the temporary wafer, preferably through a temporary adhesive layer. The tiles comprise a carrier portion and an active material portion. The active material portion is attached to the temporary carrier. The assembly further comprises a single continuous layer of the first material surrounding each of the one or more tiles. Then the back side of the carrier portions of the tiles and of the continuous layer of the first material are simultaneously planarized, and the planarized back sides of the tiles and of the continuous layer of the first material are bonded to a permanent carrier wafer, after which the temporary carrier wafer is removed.

Abstract: The embodiments herein describe authenticating a photomask used to fabricate an IC or a wafer. Because the IC may have been fabricated at a third-party IC manufacturer, the customer may want to ensure the manufacturer did not mistakenly use an incorrect mask, or that the mask was not altered or replaced with a rogue mask by a nefarious actor. That is, the embodiments herein can be used to identify when an IC manufacture (whether trusted or not) mistakenly used the wrong photomask, or to verify that a third-party IC manufacturer did not tamper with or replace the authentic photomask with a rogue mask. Advantageously, the embodiments herein can create a secure IC fabrication process to catch mistakes as well as ensure that non-trusted third-parties did not introduce defects into the IC.

Abstract: A method of forming vertical transport field effect transistor (VTFET) devices is provided. The method includes forming a plurality of vertical fins on an upper insulating layer of a dual insulator layer semiconductor-on-insulator (SeOI) substrate, and forming two masking blocks on the plurality of vertical fins, wherein a portion of a protective layer and a fin template on each of the plurality of vertical fins is exposed between the two masking blocks. The method further includes removing a portion of the upper insulating layer between the two masking blocks to form a first cavity beneath the plurality of vertical fins, and forming a first bottom source/drain in the first cavity below the plurality of vertical fins. The method further includes replacing the two masking blocks with a masking layer patterned to have two mask openings above portions of the upper insulating layer adjacent to the first bottom source/drain.

Abstract: A back-end-of-line (BEOL) component includes a substrate and a first layer of dielectric material arranged on the substrate. The first layer of dielectric material includes openings. The BEOL component further includes a first layer of metal material arranged in the openings. The BEOL component further includes an etch stop layer arranged on top of the first layer of dielectric material. The BEOL component further includes a second layer of metal material in direct contact with the first layer of metal material. The second layer of metal material includes at least one projection extending above the etch stop layer. The BEOL component further includes a second layer of dielectric material arranged on top of the etch stop layer and surrounding the at least one projection.

Abstract: Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip includes a substrate. The semiconductor chip includes multiple devices formed on the substrate. Each device includes multiple fins. A gate is formed on the multiple fins with a gate cut (CT) design that results in random distribution of complete gate cut and incomplete gate cut for each of the multiple devices based on a natural process variation in semiconductor manufacturing for each device. A physical unclonable function (PUF) region is defined in accordance with the random distribution.

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.