Abstract: A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material on the substrate, thereby forming a channel; filling a top portion of the channel with an intermediate implant forming a vertically bi-modal dopant distribution, with one doping concentration peak in the top portion of the channel and another doping concentration peak in the punch through stopper; and patterning fins into the channel and the punch though stopper to form a finFET structure.

Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.

Abstract: A method for fabricating a semiconductor structure. The method includes forming a plurality of mandrel structures. A plurality of first spacers is formed on sidewalls of the mandrel structures. A plurality of second spacers is formed on sidewalls of the first spacers. The plurality of first spacers is removed selective to the plurality of second spacers and mandrel structures. A cut mask is formed over a first set of second spacers in the plurality of second spacers and a first set of mandrel structures in the plurality of mandrel structures. A second set of second spacers in the plurality of spacers and a second set of mandrel structures in the plurality of mandrel structures remain exposed. One of the second set of mandrel structures and the second set of second spacers is removed selective to the second set of second spacers and the second set of mandrel structures, respectively.

Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.

Abstract: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

Abstract: A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fins are formed in the first region of the wafer using a variety of wet and/or dry etching procedures. The protective conformal mask layer protects the plurality of fins in the second region from the variety of wet and/or dry etching procedures that are used to form the plurality of fins in the first region.

Abstract: A method for fabricating a semiconductor structure. The method includes forming a plurality of mandrel structures. A plurality of first spacers is formed on sidewalls of the mandrel structures. A plurality of second spacers is formed on sidewalls of the first spacers. The plurality of first spacers is removed selective to the plurality of second spacers and mandrel structures. A cut mask is formed over a first set of second spacers in the plurality of second spacers and a first set of mandrel structures in the plurality of mandrel structures. A second set of second spacers in the plurality of spacers and a second set of mandrel structures in the plurality of mandrel structures remain exposed. One of the second set of mandrel structures and the second set of second spacers is removed selective to the second set of second spacers and the second set of mandrel structures, respectively.

Abstract: Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided.

Abstract: A semiconductor device includes a fin structure comprising a cylindrical shape and including a recess formed in an upper surface of the fin structure, an inner gate formed inside the fin structure, an outer gate formed outside the fin structure, and a conductor formed in the recess and connecting the inner and outer gates.

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract: A semiconductor structure includes a stained fin, a gate upon the strain fin, and a spacer upon a sidewall of the gate and upon an end surface of the strained fin. The end surface of the strained fin is coplanar with a sidewall of the gate. The spacer limits relaxation of the strained fin.

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Abstract: We disclose semiconductor devices, comprising a semiconductor substrate comprising a substrate material; and a plurality of fins disposed on the substrate, each fin comprising a lower region comprising the substrate material, a dopant region disposed above the lower region and comprising at least one dopant, and a channel region disposed above the dopant region and comprising a semiconductor material, wherein the channel region comprises less than 1×1018 dopant molecules/cm3, as well as methods, apparatus, and systems for fabricating such semiconductor devices.

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

Abstract: A method for fabricating a semiconductor device comprises patterning a strained fin from a strained layer of semiconductor material arranged on a substrate, depositing a first layer of semiconductor material on the fin and exposed portions of the substrate, patterning and etching to remove a portion of the first layer of semiconductor material and a portion of the fin to expose a portion of the substrate, depositing a second layer of semiconductor material on exposed portions of the substrate and the first layer of semiconductor material, and patterning and etching to remove a portion of the second layer of semiconductor material layer and the first layer of semiconductor material to define a dummy gate stack, the dummy gate stack is operative to substantially maintain the strain in the strained fin.