Abstract: An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

Abstract: A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for displaying navigation routes. The method includes: receiving, from a navigation server, at least two navigation routes from a navigation starting point to a navigation destination; determining a current navigation route from the navigation routes according to selection by a user, and assigning remaining routes as backup navigation routes; and displaying, in a navigation map, the current navigation route in a first mode and displaying the backup navigation routes in a second mode different from the first mode. In the embodiments of the present disclosure, by using the technical solution, the user may clearly and conveniently distinguish the current navigation route from the backup navigation routes, thereby improving the user experience.

Abstract: Technologies are described for semiconductor radiation detectors. The semiconductor radiation detectors may comprise a semiconductor material. The semiconductor material may include a first surface and a second surface. The first surface may be opposite from the second surface. The semiconductor material may include at least one metal component. The semiconductor material may be effective to absorb radiation and induce a current pulse in response thereto. The semiconductor radiation detector may comprise an electrode contact. The electrode contact may include a metal doped oxide deposited on the first surface of the semiconductor material. The metal doped oxide may include the metal component element of the semiconductor material.

Abstract: Systems and methods for selecting a neural network for a machine learning problem are disclosed. A method includes accessing an input matrix. The method includes accessing a machine learning problem space associated with a machine learning problem and multiple untrained candidate neural networks for solving the machine learning problem. The method includes computing, for each untrained candidate neural network, at least one expressivity measure capturing an expressivity of the candidate neural network with respect to the machine learning problem. The method includes computing, for each untrained candidate neural network, at least one trainability measure capturing a trainability of the candidate neural network with respect to the machine learning problem. The method includes selecting, based on the at least one expressivity measure and the at least one trainability measure, at least one candidate neural network for solving the machine learning problem.

Abstract: Embodiments of the present disclosure disclose a method, apparatus and device for displaying an emblem in navigation and a medium, and relates to a field of navigation. The method includes: obtaining current information of a navigation terminal, in which, the current information at least includes a state of a location system, a driving speed and a driving location; and drawing an emblem with the driving speed drawn thereon when the state of the location system indicates an enabled state, and displaying the emblem at the driving location. The method, apparatus and device for displaying the emblem in navigation and the medium provided by the present disclosure may reduce a display area occupied by information and solve the problem that the display area of the driving speed overlays the map elements below it while displaying the same amount of information.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for displaying navigation routes. The method includes: receiving, from a navigation server, at least two navigation routes from a navigation starting point to a navigation destination; determining a current navigation route from the navigation routes according to selection by a user, and assigning remaining routes as backup navigation routes; and displaying, in a navigation map, the current navigation route in a first mode and displaying the backup navigation routes in a second mode different from the first mode. In the embodiments of the present disclosure, by using the technical solution, the user may clearly and conveniently distinguish the current navigation route from the backup navigation routes, thereby improving the user experience.

Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

Abstract: Technologies are described for semiconductor radiation detectors. The semiconductor radiation detectors may comprise a semiconductor material. The semiconductor material may include a first surface and a second surface. The first surface may be opposite from the second surface. The semiconductor material may include at least one metal component. The semiconductor material may be effective to absorb radiation and induce a current pulse in response thereto. The semiconductor radiation detector may comprise an electrode contact. The electrode contact may include a metal doped oxide deposited on the first surface of the semiconductor material. The metal doped oxide may include the metal component element of the semiconductor material.

Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

Abstract: A clothing or garment accessory incorporating a computing platform being configured to provide a user with a wearable open computing platform. The computing platform includes a multiplicity of conductive threads incorporated in the fabric of the clothing or garment accessory used as power wires, communication wires and connection points. A central processing unit control the functions of units connected to the platform. A display unit senses a touch of a user and display executed software applications. A battery unit supplies power to the central processing unit, the display unit, and other hardware units connected to the central processing unit through the power wires. A preconfigured software app running on the central processing unit provides a user interface operable to control and communicate with the connected hardware units.

Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

Abstract: A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.

Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.

Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.