Patents by Inventor Ge Yang

Ge Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130126746
    Abstract: A novel radiation detector system is disclosed that solves the electron trapping problem by optimizing shielding of the individual virtual Frisch-grid detectors in an array configuration.
    Type: Application
    Filed: May 2, 2011
    Publication date: May 23, 2013
    Applicant: BROOKHAVEN SCIENCE ASSOCIATES, LLC
    Inventors: Aleksey E. Bolotnikov, Ge Yang, Giuseppe Camarda, Yonggang Cui, Anwar Hossain, Ki Hyun Kim, Ralph B. James
  • Publication number: 20110272589
    Abstract: The present invention relates to a novel hybrid anode configuration for a radiation detector that effectively reduces the edge effect of surface defects on the internal electric field in compound semiconductor detectors by focusing the internal electric field of the detector and redirecting drifting carriers away from the side surfaces of the semiconductor toward the collection electrode(s).
    Type: Application
    Filed: May 2, 2011
    Publication date: November 10, 2011
    Applicant: Brookhaven Science Associates, LLC
    Inventors: Ge Yang, Aleksey E. Bolotnikov, Giuseppe Camarda, Yonggang Cui, Anwar Hossain, Ki Hyun Kim, Ralph B. James
  • Patent number: 7839170
    Abstract: One embodiment of the present invention sets forth a technique for shifting the voltage level of signals from a low voltage domain to a high voltage domain, where VDDH is the supply voltage of the high voltage domain and VDDL is the supply voltage of the low voltage domain. A level shifting circuit uses a single input rather than dual rail inputs and does not produce a direct current flow in order to reduce the power consumption. The voltage level shifting circuit may also be used to shift a clock signal since the delays of the rising and falling edges of the clock signal are matched by using a delay element.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: November 23, 2010
    Assignee: NVIDIA Corporation
    Inventors: Ge Yang, Hwong-Kwo Lin, Charles Chew-Yuen Young
  • Patent number: 7830175
    Abstract: An apparatus includes a single-rail input connected to a low-voltage domain and a voltage-transition circuit connected to the single-rail input. The voltage-transition circuit is configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage of the high-voltage domain.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: November 9, 2010
    Assignee: Nvidia Corporation
    Inventors: Hwong-Kwo Lin, Ge Yang, Charles Chew-Yuen Young
  • Patent number: 7772891
    Abstract: Apparatuses and methods are provided for a self-timed dynamic sense amplifier flop circuit, wherein a pulse generating circuit may be adapted to generate at least a first logic signal based, at least in part, on a first evaluation node signal, and a discharge path circuit comprising at least a first transistor within a first stack of transistors may be operatively responsive to the first timing signal.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: August 10, 2010
    Assignee: Nvidia Corporation
    Inventors: Ge Yang, Guoqing Ning, Beibei Ren, Hwong-Kwo (Hank) Lin, Charles Chew-Yuen Young
  • Patent number: 7772885
    Abstract: One embodiment of the present invention sets forth a technique for shifting the voltage level of signals from the high voltage domain to a low voltage domain, where VDD_IO is the supply voltage of the high voltage domain and VDD_Logic is the supply voltage of the low voltage domain. A level shifting circuit using a combination of I/O and logic transistors avoids exceeding a maximum tolerable voltage across the gate and source of any of the transistors. The level shifting circuit operates includes a reference voltage circuit that is independent of VDD_IO, so the same level shifting circuit may be used for various VDD_IO voltages. Additionally, the voltage level shifting circuit is not sensitive to scaling of VDD_Logic and operates properly when VDD_Logic is reduced due to shrinking silicon process technology and/or is reduced for a low power application.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: August 10, 2010
    Assignee: NVIDIA Corporation
    Inventors: Hwong-Kwo Lin, Ge Yang, Guoqing Ning, Charles Chew-Yuen Young
  • Patent number: 7768320
    Abstract: One embodiment of the present invention sets forth a sense amplifier flop design that is tolerant of process variation. Specific staging of signal transitions through the sense amplifier flop circuit eliminate operational phases involving short-circuit currents between n-channel field-effect transistors (N-FETs) and p-channel field effect transistors (P-FETs) in a complementary-symmetry metal-oxide semiconductor process. By eliminating short-circuit currents between N-FETs and P-FETs within the sense amplifier flop, a large variation in conductivity ratio between N-FETs and P-FETs may be tolerated by the sense amplifier flop. This tolerance to conductivity ratio translates to a tolerance for process variation by the sense amplifier flop circuit.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: August 3, 2010
    Assignee: NVIDIA Corporation
    Inventors: Ge Yang, Hwong-Kwo Lin, Charles Chew-Yuen Young
  • Patent number: 7649762
    Abstract: Embodiments for an area efficient high performance memory cell comprising a transistor connected to one of a bit line and a bit line bar are disclosed.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: January 19, 2010
    Assignee: nVidia Corporation
    Inventors: Hwong-Kwo Lin, Ge Yang, Charles Chew-Yuen Young
  • Patent number: 7643330
    Abstract: One embodiment of the present invention sets forth a synchronous two-port static random access memory (SRAM) design with the area efficiency of a one-port SRAM. By restricting both access ports to an edge-triggered, synchronous clocking regime, the internal timing of the SRAM can be optimized to allow high-performance double-pumped access to the SRAM storage cells. By double-pumping the SRAM storage cells, one read access and one write access are possible per clock cycle, allowing the SRAM to present two external ports, each capable of performing one transaction per clock cycle.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: January 5, 2010
    Assignee: NVIDIA Corporation
    Inventors: Hwong-Kwo Lin, Ge Yang, Ethan A. Frazier, Charles Chew-Yuen Young
  • Patent number: 7626871
    Abstract: One embodiment of the present invention sets forth a high-speed single-ended memory read circuit that overcomes performance limitations of conventional single ended memory read circuits. A bit line keeper control mechanism for the high-speed single-ended memory read circuit is disclosed that automatically configures the bit line keeper for high-speed operation or low-speed operation, based on the frequency of a system clock. In high-speed operation, the bit line keeper is disabled, thereby eliminating short-circuit currents related to the bit line keeper and increasing the read performance of the single-ended memory read circuit. In low-speed operation, the bit line keeper is periodically disabled by a timer circuit to enable efficient read or write operations. Subsequent to the read or write operation, the bit line keeper is enabled to preserve state on the bit lines. By selectively enabling the bit line keeper, high-speed performance is improved while preserving correct function at low speeds.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: December 1, 2009
    Assignee: NVIDIA Corporation
    Inventors: Ge Yang, Hwong-Kwo (Hank) Lin, Charles Chew-Yuen Young
  • Patent number: 7626854
    Abstract: One embodiment of the present invention sets forth a twelve transistor static random access memory storage cell that provides two write ports and three read ports. The write word line operates at twice the clock frequency. The write bit lines are differential to provide high-performance writes. Each read word line operates at the clock frequency. Single-ended read bit lines are used to provide read performance comparable to write performance. The resulting storage cell only requires four horizontal word lines and five vertical bit lines, enabling very dense, yet high-performance designs.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: December 1, 2009
    Assignee: NVIDIA Corporation
    Inventors: Ge Yang, Hwong-Kwo (Hank) Lin, Charles Chew-Yuen Young
  • Patent number: 7626878
    Abstract: One embodiment of the present invention sets forth an active bit line charge keeper circuit for improving the reliability of a static random access memory (SRAM) circuit. The active bit line charge keeper circuit includes two sub-circuits, each disposed between bit line pairs within the SRAM circuit. The first sub-circuit mitigates residual state associated with over-developed read state on the bit lines. The second sub-circuit mitigates the effects of residual state associated with reading one value on a given pair of bit lines and subsequently writing a different value. By mitigating the effects of residual state within an SRAM circuit, higher reliability at a given performance level may be achieved.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: December 1, 2009
    Assignee: NVIDIA Corporation
    Inventors: Hwong-Kwo Lin, Ge Yang, Ethan A. Frazier, Charles Chew-Yuen Young
  • Patent number: 7583126
    Abstract: An apparatus and method are provided for preventing a current leakage or direct current when a low voltage domain is powered down. Included is a voltage transition circuit connected between a low voltage domain and a high voltage domain. Such voltage transition circuit includes a circuit component for preventing a current leakage when the low voltage domain is powered down.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: September 1, 2009
    Assignee: NVIDIA Corporation
    Inventors: Ge Yang, Hwong-Kwo Lin, Charles Chew-Yuen Young
  • Patent number: 7504872
    Abstract: One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: March 17, 2009
    Assignee: NVIDIA Corporation
    Inventors: Hwong-Kwo Lin, Ge Yang, Ethan A. Frazier, Charles Chew-Yuen Young
  • Publication number: 20090045847
    Abstract: One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.
    Type: Application
    Filed: August 13, 2007
    Publication date: February 19, 2009
    Inventors: Hwong-Kwo Lin, Ge Yang, Ethan A. Frazier, Charles Chew-Yuen Young
  • Patent number: 7492204
    Abstract: One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: February 17, 2009
    Assignee: NVIDIA Corporation
    Inventors: Hwong-Kwo Lin, Ge Yang, Ethan A. Frazier, Charles Chew-Yuen Young
  • Patent number: 7463065
    Abstract: An apparatus includes a single-rail input connected to a low-voltage domain and a voltage-transition circuit connected to the single-rail input. The voltage-transition circuit is configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage of the high-voltage domain.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: December 9, 2008
    Assignee: NVIDIA Corporation
    Inventors: Hwong-Kwo Lin, Ge Yang, Charles Chew-Yuen Young
  • Publication number: 20080290935
    Abstract: An apparatus and method are provided for preventing a current leakage or direct current when a low voltage domain is powered down. Included is a voltage transition circuit connected between a low voltage domain and a high voltage domain. Such voltage transition circuit includes a circuit component for preventing a current leakage when the low voltage domain is powered down.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 27, 2008
    Inventors: Ge Yang, Hwong-Kwo Lin, Charles Chew-Yuen Young
  • Publication number: 20080260592
    Abstract: A pipettor is provided of discretely adjusting the volume of fluid transferable by the pipettor in a pipetting operation. One or multiple piston assemblies, comprising pistons detached from the actuator of the pipettor, resilient members that urges the pistons toward initial positions, and independent adjusting mechanisms, such as slide-and-lock, facilitate discrete adjustments of the pipetting volume. The pipettor affords the operator to expediently adjust the pipetting volume, and to conveniently operate the pipettor using only one hand.
    Type: Application
    Filed: February 12, 2008
    Publication date: October 23, 2008
    Inventors: Zhenggang Yang, Ge Yang
  • Patent number: 7304508
    Abstract: Embodiments related to fast flip-flops are disclosed.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: December 4, 2007
    Inventors: Ge Yang, Hank Lin, Charles Young