Patents by Inventor Gene Lee

Gene Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9892485
    Abstract: A method of manipulating at least a portion of a character model into a pose involving a library data having a plurality of deformations, where each deformation is associated with index values of one or more distance measurement nodes. One or more distance measurement nodes are defined for the portion of the character model, wherein each distance measurement node comprises a number of points on a surface defined by the geometry of the character model, wherein the points are separated by a distance value. A particular pose is selected for the character model portion to establish an initial model by selecting values for the pose controls. For the particular pose, a value of the distance measurement nodes is determined. At least one deformation is selected from the library data based in the value of the distance measurement nodes and applied to the initial model to generate a deformed model.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: February 13, 2018
    Assignee: Disney Enterprises, Inc.
    Inventors: Clay Kaytis, John Edgar Park, Gene Lee, Philippe Brochu, Hidetaka Yosumi
  • Patent number: 9889212
    Abstract: A preparation method for a magnetic composite for treating and diagnosing cancer. The method may include a step of pyrolyzing a precursor of a magnetic nanoparticle in the presence of a conjugated polymer. The preparation method for a magnetic composite can produce a magnetic composite economically and efficiently because a magnetic composite comprising a magnetic nanoparticle coated with a conjugated polymer can be prepared by a single process.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: February 13, 2018
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Jae Moon Yang, Jin Suck Suh, Seung Joo Haam, Eu Gene Lee, Yoo Chan Hong, Min Hee Ku, Dan Heo, Seung Yeon Hwang, Yong Min Huh
  • Publication number: 20180025914
    Abstract: Methods for etching a bottom anti-reflective coating (BARC) and/or an anti-reflective coating (ARC) and/or a dielectric anti-reflective coating (DARC) to form high aspect ratio features using an etch process are provided. The methods described herein advantageously facilitate profile and dimension control of features with high aspect ratios through a proper sidewall and bottom management scheme during the bottom anti-reflective coating (BARC) and/or an anti-reflective coating (ARC) and/or a dielectric anti-reflective coating (DARC) open process.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 25, 2018
    Inventors: Hailong ZHOU, Gene LEE, Abhijit PATIL, Shan JIANG, Akhil MEHROTRA, Jonathan KIM
  • Patent number: 9852923
    Abstract: A hard mask layer is deposited on a feature layer over a substrate. The hard mask layer comprises an organic mask layer. An opening in the organic mask layer is formed using a first gas comprising a halogen element at a first temperature greater than a room temperature to expose a portion of the feature layer. In one embodiment, a gas comprising a halogen element is supplied to a chamber. An organic mask layer on an insulating layer over a substrate is etched using the halogen element at a first temperature to form an opening to expose a portion of the insulating layer.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: December 26, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Gene Lee, Lucy Chen
  • Publication number: 20170322262
    Abstract: State of health processes and systems are provided for analyzing a capacitor, such as a supercapacitor. The process includes, for instance: determining a measured capacitance of a capacitor; estimating an effective series resistance (ESR) of the capacitor; determining, using the measured capacitance and the effective series resistance, a linearized capacitance parameter (CAP) for the capacitor; and signaling should the CAP drop below, or the ESR rise above, a respective specified threshold for the capacitor. Using the CAP and the effective series resistance, an amount of energy remaining in the capacitor may be determined, upon which to base one or more actions.
    Type: Application
    Filed: May 4, 2017
    Publication date: November 9, 2017
    Applicant: The Paper Battery Company, Inc.
    Inventor: Gene Lee ARMSTRONG, II
  • Patent number: 9746725
    Abstract: A liquid crystal display, includes: a substrate; a gate line including a gate pad and a data line including a data pad, the gate and data lines being disposed on the substrate; a thin film transistor connected to the gate line and the data line; an organic layer disposed on the thin film transistor; a pixel electrode disposed on the organic layer; a first contact assistant disposed on the gate pad; a second contact assistant disposed on the data pad; a first insulating layer disposed on the pixel electrode; and a common electrode disposed on the first insulating layer, the common electrode overlapping with the pixel electrode. The common electrode includes first cutouts, the first insulating layer includes second cutouts, the plane shapes of the first and second cutouts are substantially the same, and the pixel electrode includes a polycrystalline transparent conductive material.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: August 29, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hwa Yeul Oh, Sung Man Kim, Young Je Cho, Min-Chul Song, Eu Gene Lee, Soo Jung Chae, Hyun Ki Hwang
  • Patent number: 9671658
    Abstract: A liquid crystal display includes a substrate, a plurality of signal lines, a gate driver, and a sealant. The substrate includes a display area and a peripheral area outside the display area. The signal lines are integrated with the substrate and include a clock signal line. The gate driver includes a stage located between the clock signal line and the display area. The stage is integrated with the substrate and is configured to apply a gate voltage to the display area. The sealant is distributed over part of the peripheral area. A seal region where the sealant is distributed includes a seal line, and the clock signal line is located within the seal line. The clock signal line is located further away from the stage than the other signal lines.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: June 6, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sung-Hoon Lim, Man Hong Na, Young-Je Cho, Sung-Man Kim, Min-Chul Song, Soo Jung Chae, Eu Gene Lee
  • Patent number: 9666611
    Abstract: A thin film transistor array panel includes: a data line which extends in a column direction and transfers a data voltage; a first pixel electrode and a second pixel electrode connected to the data line and adjacent in a row direction; a first thin film transistor connected to the first pixel electrode and the data line, and including a first source electrode and a first drain electrode; and a second thin film transistor connected to the second pixel electrode and the data line, and including a second source electrode and a second drain electrode. The first pixel electrode is at the right of the data line, the second pixel electrode is at the left of the data line, and relative positions of the first source electrode and the first drain electrode are the same as relative positions of the second source electrode and the second drain electrode.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 30, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Min-Chul Song, Man Hong Na, Young Je Cho, Sung Man Kim, Sung-Hoon Lim, Soo Jung Chae, Eu Gene Lee
  • Patent number: 9644185
    Abstract: A method of preparing a reprogramming induced pluripotent stem cell from a human-derived somatic cell using a fusion protein in which a reprogramming inducing factor and cell permeable peptide (CPP) are fused, and a fusion protein in which a reprogramming inducing factor and a cell permeable peptide are fused are disclosed. According to the present invention, the induced pluripotent stem cell having high efficiency and high stability can be prepared by maximizing the effect of the reprogramming inducing transcription factor beyond the existing viral peptide transporter, in inducing the reprogramming of the somatic cell.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: May 9, 2017
    Assignees: SNU R&DB FOUNDATION, NANO INTELLIGENT BIOMEDICAL ENGINEERING CORPORATION CO. LTD.
    Inventors: Yoon Jeong Park, Gene Lee, Hyun Nam, Jin Sook Suh, Chong-Pyoung Chung, Jue-Yeon Lee
  • Patent number: 9613456
    Abstract: Methods and systems for two-phase skinning of an object undergoing rigid and non-rigid transformations are disclosed. One method of skinning the object may include separating the object's joint transformations into rigid and non-rigid parts by determining if a joint is scale compensating or scale non-compensating, applying non-rigid joint transformations to the mesh, and applying rigid joint transformations to the mesh. Separation of the object's joint transformations into rigid and non-rigid parts may include determining a bind pose based on an initial configuration of the object's joints and determining an intermediate pose based on the configuration of the object's joints after non-rigid joint transformations are applied to the joints.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: April 4, 2017
    Assignee: DISNEY ENTERPRISES, INC.
    Inventors: Gene Lee, Chung-An Lin
  • Patent number: 9595451
    Abstract: Methods for forming high aspect ratio features using an etch process are provided. In one embodiment, a method for etching a dielectric layer to form features in the dielectric layer includes (a) supplying an etching gas mixture during a first mode to etch a portion of a dielectric layer disposed on a substrate while forming a passivation protection in the dielectric layer, wherein the dielectric layer is etched through openings defined in a patterned mask layer disposed on the dielectric layer, (b) supplying an etching gas mixture during a second mode to continue forming the passivation protection in the dielectric layer without etching the dielectric layer, and repeatedly performing (a) and (b) to form features in the dielectric layer until a surface of the substrate is exposed.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: March 14, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Hailong Zhou, Gene Lee, Liming Yang
  • Publication number: 20170056533
    Abstract: A preparation method for a magnetic composite for treating and diagnosing cancer. The method may include a step of pyrolyzing a precursor of a magnetic nanoparticle in the presence of a conjugated polymer. The preparation method for a magnetic composite can produce a magnetic composite economically and efficiently because a magnetic composite comprising a magnetic nanoparticle coated with a conjugated polymer can be prepared by a single process.
    Type: Application
    Filed: February 17, 2015
    Publication date: March 2, 2017
    Applicant: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Jae Moon Yang, Jin Suck Suh, Seung Joo Haam, Eu Gene Lee, Yoo Chan Hong, Min Hee Ku, Dan Heo, Seung Yeon Hwang, Yong Min Huh
  • Publication number: 20170063106
    Abstract: Charge processes and systems are provided for charging a supercapacitor. The charging includes: charging a supercapacitor by applying a constant charge to the supercapacitor; and controlling termination of the constant charging of the supercapacitor. In one approach, the controlling termination includes dynamically determining, during the charging, a remaining charge time for the constant charging to substantially fully charge the supercapacitor; and allowing the charging to continue for the remaining charge time, and based on expiration of the remaining charge time, terminating the charging.
    Type: Application
    Filed: August 19, 2016
    Publication date: March 2, 2017
    Applicant: THE PAPER BATTERY COMPANY, INC.
    Inventor: Gene Lee ARMSTRONG
  • Publication number: 20160319357
    Abstract: Systems and methods for detecting at least two genomic alleles associated with corneal dystrophy in a sample from a human subject are disclosed in which cells (e.g., epithelial) of the subject are adhered to a tip of a substrate. The tip of the substrate is agitated in a lysis solution that lyses cells adhered to the substrate. The substrate is removed from the lysis solution upon completion of this agitation. The resulting lysis solution is incubated and then genomic DNA from the lysis solution is isolated to form a gDNA solution. From this, identity of at least two nucleotides present in the human TGF?I gene is determined using at least two oligonucleotide primer pairs and the gDNA solution. These at least two nucleotides are located at respective independent positions of the TGF?I gene corresponding to respective independent single nucleotide polymorphisms (SNPs) associated with corneal dystrophy.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 3, 2016
    Inventors: Connie CHAO-SHERN, Sun-Young CHO, Gene LEE
  • Patent number: 9476064
    Abstract: An embryonic stem cell line derived from a nucleus-transferred oocyte prepared by transferring a nucleus of a human somatic cell into an enucleated human oocyte may differentiate into various desired cell types.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 25, 2016
    Assignee: H BION CO., LTD.
    Inventors: Sung-Il Roh, Woo-Suk Hwang, Byeong-Chun Lee, Sung-Keun Kang, Young-June Ryu, Eu-Gene Lee, Soon-Woong Kim, Dae-Kee Kwon, Hee-Sun Kwon, Ja-Min Koo, Eul-Soon Park, Youn-Young Hwang, Hyun-Soo Yoon, Jong-Hyuk Park, Sun-Jong Kim
  • Publication number: 20160293441
    Abstract: A hard mask layer is deposited on a feature layer over a substrate. The hard mask layer comprises an organic mask layer. An opening in the organic mask layer is formed using a first gas comprising a halogen element at a first temperature greater than a room temperature to expose a portion of the feature layer. In one embodiment, a gas comprising a halogen element is supplied to a chamber. An organic mask layer on an insulating layer over a substrate is etched using the halogen element at a first temperature to form an opening to expose a portion of the insulating layer.
    Type: Application
    Filed: April 2, 2015
    Publication date: October 6, 2016
    Inventors: Gene Lee, Lucy Chen
  • Patent number: 9377655
    Abstract: A liquid crystal display includes: a first insulation substrate; a first gate conductor disposed on the first insulation substrate and in a same layer as a gate line and a second gate conductor disposed on the first insulation substrate and in the same layer as the gate line; a gate insulating layer disposed on the first gate conductor and the second gate conductor; a data conductor disposed on the gate insulating layer and in a same layer as a data line; a thin film transistor disposed on the first insulation substrate; a first spacer disposed on the first insulation substrate; and a second spacer disposed on the first insulation substrate, where heights or widths of the first and second spacers are different from each other and having different heights or widths, and the second spacer overlaps the first gate conductor and the second gate conductor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 28, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sung Man Kim, Sung Hoon Kim, Man Hong Na, Min-Chul Song, Jun Ho Song, Eu Gene Lee, Sung-Hoon Lim, Young Je Cho, Sun-Kyu Joo, Soo Jung Chae
  • Publication number: 20160134666
    Abstract: Disclosed herein are system, apparatus, method and/or computer program product embodiments for providing survivable calling and conferencing. An embodiment operates by providing, by a first server, a first sub-conference to a plurality of user devices over first lines. The first sub-conference is combined with a second sub-conference to form a collective conference of the plurality of user devices. The first server accesses the conference. A second server is configured to provide the second sub-conference of the collective conference to the plurality of user devices over second lines, the first and second lines being distinct from each other. The collective conference may provide resilient and reliable sharing of information among participants and may leverage dispersed elements or diverse links simultaneously without impediments of echoes, loops, or other impacts.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 12, 2016
    Applicant: The MITRE Corporation
    Inventors: Randall Paul Joseph Ethier, Gene Lee Harrison
  • Patent number: 9299580
    Abstract: Embodiments of the present disclosure provide methods for forming features in a film stack that may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method of etching a material layer disposed on a substrate using synchronized RF pulses includes providing an etching gas mixture into a processing chamber having a film stack disposed on a substrate, synchronously pulsing a RF source power and a RF bias power into the etching gas mixture at a ratio of less than 0.5, and etching the film stack disposed on the substrate.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: March 29, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Byungkook Kong, Gene Lee, Liming Yang
  • Publication number: 20160085106
    Abstract: A liquid crystal display includes a substrate, a plurality of signal lines, a gate driver, and a sealant. The substrate includes a display area and a peripheral area outside the display area. The signal lines are integrated with the substrate and include a clock signal line. The gate driver includes a stage located between the clock signal line and the display area. The stage is integrated with the substrate and is configured to apply a gate voltage to the display area. The sealant is distributed over part of the peripheral area. A seal region where the sealant is distributed includes a seal line, and the clock signal line is located within the seal line. The clock signal line is located further away from the stage than the other signal lines.
    Type: Application
    Filed: December 2, 2015
    Publication date: March 24, 2016
    Inventors: SUNG-HOON LIM, MAN HONG NA, YOUNG-JE CHO, SUNG-MAN KIM, MIN-CHUL SONG, SOO JUNG CHAE, EU GENE LEE