Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap contact connector.

Abstract: Systems, methods and aspects, and embodiments thereof relate to unsupervised or semi-supervised features learning using a quantum processor. To achieve unsupervised or semi-supervised features learning, the quantum processor is programmed to achieve Hierarchal Deep Learning (referred to as HDL) over one or more data sets. Systems and methods search for, parse, and detect maximally repeating patterns in one or more data sets or across data or data sets. Embodiments and aspects regard using sparse coding to detect maximally repeating patterns in or across data. Examples of sparse coding include L0 and L1 sparse coding. Some implementations may involve appending, incorporating or attaching labels to dictionary elements, or constituent elements of one or more dictionaries. There may be a logical association between label and the element labeled such that the process of unsupervised or semi-supervised feature learning spans both the elements and the incorporated, attached or appended label.

Abstract: Systems, devices, and methods for using an analog processor to solve computational problems. A digital processor is configured to track computational problem processing requests received from a plurality of different users, and to track at least one of a status and a processing cost for each of the computational problem processing requests. An analog processor, for example a quantum processor, is operable to assist in producing one or more solutions to computational problems identified by the computational problem processing requests via a physical evolution.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: Quantum processor based techniques minimize an objective function for example by operating the quantum processor as a sample generator providing low-energy samples from a probability distribution with high probability. The probability distribution is shaped to assign relative probabilities to samples based on their corresponding objective function values until the samples converge on a minimum for the objective function. Problems having a number of variables and/or a connectivity between variables that does not match that of the quantum processor may be solved. Interaction with the quantum processor may be via a digital computer. The digital computer stores a hierarchical stack of software modules to facilitate interacting with the quantum processor via various levels of programming environment, from a machine language level up to an end-use applications level.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.

Abstract: A method of improving the accuracy and computation time of automatic image recognition by the implementation of association graphs and a quantum processor. A method of solving problems using a quantum processor by casting a problem as a quadratic unconstrained binary optimization (“QUBO”) problem, mapping the QUBO problem to the quantum processor, and evolving the quantum processor to produce a solution to the QUBO problem.

Abstract: Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.

Abstract: Systems, methods and apparatus for factoring numbers are provided. The factoring may be accomplished by creating a factor graph, mapping the factor graph onto an analog processor, initializing the analog processor to an initial state, evolving the analog processor to a final state, and receiving an output from the analog processor, the output comprising a set of factors of the number. The factoring may be accomplished by generating a logic circuit representation of the factoring problem, such as a multiplication circuit, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s).

Abstract: Cryogenic refrigeration employs a pulse tube cryo-cooler and a dilution refrigerator to provide very low temperature cooling, for example, to cool superconducting processors. Continuous cryogenic cycle refrigeration may be achieved using multiple adsorption pumps. Various improvements may include multiple distinct thermal-linking points, evaporation pots with cooling structures, and/or one or more gas-gap heat switches which may be integral to an adsorption pump. A reservoir volume may provide pressure relief when the system is warmed above cryogenic temperature, reducing the mass of the system. Additional heat exchangers and/or separate paths for condensation and evaporation may be provided. Multi-channel connectors may be used, and/or connectors formed of a regenerative material with a high specific heat capacity at cryogenic temperature. Flexible PCBs may provide thermal links to components that embody temperature gradients.

Abstract: Iterative approaches to quantum computation are described. Incongruities in the behavior of the various individual elements in a quantum processor may be managed by establishing a set of equivalent configurations for the elements of the quantum processor. The quantum processor is programmed and operated using each equivalent configuration to determine a set of solutions. The solutions are evaluated to determine a preferred solution that best satisfies at least one criterion. Furthermore, thermodynamic effects from operating a quantum processor at non-absolute zero temperature can cause the ground state to be the most probable state into which the system will settle. By running multiple iterations the ground state may be identified as the state with the most frequent reoccurrences. Alternatively, the energy of each unique state may be calculated and the state that corresponds to the lowest energy may be returned as the solution to the problem.

Abstract: Cryogenic refrigeration employs a pulse tube cryo-cooler and a dilution refrigerator to provide very low temperature cooling, for example, to cool superconducting processors. Continuous cryogenic cycle refrigeration may be achieved using multiple adsorption pumps. Various improvements may include multiple distinct thermal-linking points, evaporation pots with cooling structures, and/or one or more gas-gap heat switches which may be integral to an adsorption pump. A reservoir volume may provide pressure relief when the system is warmed above cryo genic temperature, reducing the mass of the system. Additional heat exchangers and/or separate paths for condensation and evaporation may be provided. Multi-channel connectors may be used, and/or connectors formed of a regenerative material with a high specific heat capacity at cryogenic temperature. Flexible PCBs may provide thermal links to components that embody temperature gradients.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: Systems, devices, and methods for using an analog processor to solve computational problems. A digital processor is configured to track computational problem processing requests received from a plurality of different users, and to track at least one of a status and a processing cost for each of the computational problem processing requests. An analog processor, for example a quantum processor, is operable to assist in producing one or more solutions to computational problems identified by the computational problem processing requests via a physical evolution.

Abstract: A recursive approach to quantum computing employs an initial solution, determines intermediate solutions, evaluates the intermediate solutions and repeats using the intermediate solution, if the intermediate solution does not satisfy solution criteria. A best one of the intermediate solutions may be employed in the recursion.