Abstract: An analog processor, for example a quantum processor may include a plurality of elongated qubits that are disposed with respect to one another such that each qubit may selectively be directly coupled to each of the other qubits via a single coupling device. Such may provide a fully interconnected topology.

Abstract: Systems, devices, and methods for using an analog processor to solve computational problems. A digital processor is configured to track computational problem processing requests received from a plurality of different users, and to track at least one of a status and a processing cost for each of the computational problem processing requests. An analog processor, for example a quantum processor, is operable to assist in producing one or more solutions to computational problems identified by the computational problem processing requests via a physical evolution.

Abstract: A method of improving the accuracy and computation time of automatic image recognition by the implementation of association graphs and a quantum processor. A method of solving problems using a quantum processor by casting a problem as a quadratic unconstrained binary optimization (“QUBO”) problem, mapping the QUBO problem to the quantum processor, and evolving the quantum processor to produce a solution to the QUBO problem.

Abstract: Iterative approaches to quantum computation are described. Incongruities in the behavior of the various individual elements in a quantum processor may be managed by establishing a set of equivalent configurations for the elements of the quantum processor. The quantum processor is programmed and operated using each equivalent configuration to determine a set of solutions. The solutions are evaluated to determine a preferred solution that best satisfies at least one criterion. Furthermore, thermodynamic effects from operating a quantum processor at non-absolute zero temperature can cause the ground state to be the most probable state into which the system will settle. By running multiple iterations the ground state may be identified as the state with the most frequent reoccurrences. Alternatively, the energy of each unique state may be calculated and the state that corresponds to the lowest energy may be returned as the solution to the problem.

Abstract: Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: A method of improving the accuracy and computation time of automatic image recognition by the implementation of association graphs and a quantum processor.

Abstract: A quantum processor may employ a heterogeneous qubit-coupling architecture to reduce the average number of intermediate coupling steps that separate any two qubits in the quantum processor, while limiting the overall susceptibility to noise of the qubits. The architecture may effectively realize a small-world network where the average qubit has a low connectivity (thereby allowing it to operate substantially quantum mechanically) but each qubit is within a relatively low number of intermediate coupling steps from any other qubit. To realize such, some of the qubits may have a relatively high connectivity, and may thus operate substantially classically.

Abstract: Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

Abstract: Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.

Abstract: Systems, methods and apparatus for factoring numbers are provided. The factoring may be accomplished by creating a factor graph, mapping the factor graph onto an analog processor, initializing the analog processor to an initial state, evolving the analog processor to a final state, and receiving an output from the analog processor, the output comprising a set of factors of the number. The factoring may be accomplished by generating a logic circuit representation of the factoring problem, such as a multiplication circuit, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s).

Abstract: Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.

Abstract: Cryogenic refrigeration employs a pulse tube cryo-cooler and a dilution refrigerator to provide very low temperature cooling, for example, to cool superconducting processors. Continuous cryogenic cycle refrigeration may be achieved using multiple adsorption pumps. Various improvements may include multiple distinct thermal-linking points, evaporation pots with cooling structures, and/or one or more gas-gap heat switches which may be integral to an adsorption pump. A reservoir volume may provide pressure relief when the system is warmed above cryogenic temperature, reducing the mass of the system. Additional heat exchangers and/or separate paths for condensation and evaporation may be provided. Multi-channel connectors may be used, and/or connectors formed of a regenerative material with a high specific heat capacity at cryogenic temperature. Flexible PCBs may provide thermal links to components that embody temperature gradients.

Abstract: A quantum processor may employ a heterogeneous qubit-coupling architecture to reduce the average number of intermediate coupling steps that separate any two qubits in the quantum processor, while limiting the overall susceptibility to noise of the qubits. The architecture may effectively realize a small-world network where the average qubit has a low connectivity (thereby allowing it to operate substantially quantum mechanically) but each qubit is within a relatively low number of intermediate coupling steps from any other qubit. To realize such, some of the qubits may have a relatively high connectivity, and may thus operate substantially classically.

Abstract: A method of simulating a molecular system using a hybrid computer is provided. The hybrid computer comprises a classical computer and a quantum computer. The method uses atomic coordinates {right arrow over (R)}n and atomic charges Zn of a molecular system to compute a ground state energy of the molecular system using the quantum computer. The ground state energy is returned to the classical computer and the atomic coordinates are geometrically optimized on the classical computer based on information about the returned ground state energy of the atomic coordinates in order to produce a new set of atomic coordinates {right arrow over (R)}?n for the molecular system.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.