Abstract: An integrated memory has a normal bit line for transferring data from or to normal memory cells connected to it, and also a normal sense amplifier, which is connected via a line to the normal bit line and connected to a data line and amplifies data read from the normal memory cells. Furthermore, the memory has a redundant sense amplifier for replacing the normal sense amplifier in the redundancy situation. The redundant sense amplifier is likewise connected on the one hand to the line and on the other hand to the data line and, in the redundancy situation, serves for amplifying the data read from the normal memory cells. A method for repairing an integrated memory is also provided.

Abstract: A method is described for reading and writing a ferroelectric memory. In ferroelectric memories, changes in a hysteresis curve on account of aging of the ferroelectric material are reduced or prevented by virtue of the fact that during reading and writing a complementary state is also written in and a capacitor voltage is reduced to 0 V before a memory cell is deactivated.

Abstract: A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the surface of the channel region and forms a Schottky diode with the semiconductor substrate, and a ferroelectric layer and a gate electrode are disposed on its surface. The ferroelectric transistor is fabricated using steps appertaining to silicon process technology.

Abstract: A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.

Abstract: The memory has writable memory cells. In addition, it has a bit line pair which connects the memory cells MC to a differential sense amplifier. A control unit is used for precharging the bit lines in a plurality of steps before one of the memory cells is conductively connected to one of the bit lines for a read access operation. For a write access operation, the control unit carries out no more than some of the bit line precharging steps provided for a read access operation before the sense amplifier transfers data to the bit line pair.

Abstract: The integrated memory has driver units DRVi, via which the column select lines CSLi are connected to the plate line segments PLi and which, as a function of the potential of the associated column select lines CSLi and the word addresses RADR on the plate line segments PLi connected to them, generate potentials which have defined values for each operating state of the memory.

Abstract: A semiconductor circuit is disclosed which contains a driving circuit which is integrated into a semiconductor substrate of a first conductivity type and includes positive voltage switching transistors for switching positive and/or zero voltage levels and negative switching transistors for switching negative and/or zero voltage levels. In addition, the driving circuit contains a control circuit which is positioned upstream from the driving circuit and is also embodied in the semiconductor substrate, which is connected to a substrate voltage. A negative voltage switching transistor of the driving circuit is configured inside an outer well which is embedded in the semiconductor substrate and is of a second conductivity type which is opposite to the first, and the outer well is connected to a supply voltage.

Abstract: The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The decoder element makes it possible to produce any one of the three potentials at its output based upon the potentials on its connections.

Abstract: In a semiconductor memory configuration, a refresh operation is always started by a refresh logic circuit when a comparison circuit determines that there is a specific minimum difference when comparing a characteristic variable of at least one reference memory cell with a reference value (VREF).

Abstract: The memory cell configuration is formed with hybrid memory cells. Individual bit line pairs are isolated from one another by a respective bit line from an adjacent bit line pair, so that the memory cells are arranged relative to one another with ¼ division. This means that intrinsically cohesive implantation mask parts without connection or corner regions can be used, which avoids implantation problems and still permits production of transistors with a different threshold voltage.

Abstract: The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

Abstract: The memory device has series-connected ferroelectric memory cells in which a series circuit composed of a resistor and/or of a transistor for the ferroelectric capacitor of a respective memory cell is present. As a result, without unacceptably increasing the access time, the interference pulses at the ferroelectric capacitors of the memory cells which are not being addressed at that particular time and which are generated by the reading out or writing of the addressed memory cell are reduced in such a way that they have virtually no further influence on the non-addressed memory cells.

Abstract: A ferroelectric storage assembly containing a storage cell array composed of a plurality of storage cells is described. Each storage cell contains at least one selector transistor and a storage capacitor, and can be controlled via word lines and bit lines. A short-circuit transistor is located over each storage capacitor in order to protect the storage.

Abstract: An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.

Abstract: A method is described for reading and writing a ferroelectric memory. In ferroelectric memories, changes in a hysteresis curve on account of aging of the ferroelectric material are reduced or prevented by virtue of the fact that during reading and writing a complementary state is also written in and a capacitor voltage is reduced to 0 V before a memory cell is deactivated.

Abstract: An integrated memory having a first wiring plane with parallel conductor tracks running therein. A second wiring plane in the memory has segments running in it that are parallel to the conductor tracks. Word lines are each formed by a conductor track of a first type and by segments configured parallel to this conductor track. A conductor track of a second type is connected to a first supply line and to regions that are configured in a third wiring plane within the cell array.

Abstract: The invention relates to a memory configuration comprising a multiplicity of memory cells. Each of the memory cells has at least one ferroelectric storage capacitor and a selection transistor. The memory cells are addressed via word lines and bit line pairs. It is possible for a reference signal obtained from a reference cell pair via a bit line pair to be compared with a read signal from a memory cell in a sense amplifier. The sense amplifier is thereby assigned two bit line pairs connected in such a way that the reference signal is applied via the first bit line pair and, at the same time, the read signal is applied via the second bit line pair to the sense amplifier.

Abstract: An integrated memory includes a cell array having bit lines, word lines and writable memory cells. A first differential sense amplifier has connections connected to a data line pair through which the first sense amplifier reads information from one of the memory cells during a read access operation in order to amplify it subsequently, and through which the first sense amplifier writes information to one of the memory cells during a write access operation. The relevant information is transferred as differential signals through the data line pair and is temporarily stored by the first sense amplifier during every write access operation. The memory also has a switching unit through which the data line pair is connected to the connections of the first sense amplifier, for interchanging the lines of the data line pair in relation to the connections of the first sense amplifier, depending on the switching state of the switching unit.

Abstract: A Phillips catalyst for the polymerization of .alpha.-olefins, containing, as a catalytically active component, at least one chromium(III) compound on a silicon aluminum phosphate carrier of the general formula (I)(Si.sub.x Al.sub.y P.sub.z)O.sub.2 (I)where x is from 0.05 to 0.5 and y and z are each from 0.1 to 1.0, exhibits in particular high productivity and is preferably used for the preparation of homo- and copolymers of ethylene.

Abstract: Polymer blends containa) from 20 to 70% by weight of a propylene copolymer which in turn consists of from 20 to 65% by weight of a propylene homopolymer and 30 to 85% by weight of a random propylene copolymer containing polymerized C.sub.2 -C.sub.10 -alk-1-enes andb) from 30 to 80% by weight of a polyethylene having a density of from 0.94 to 0.98 g/cm.sup.3 and a melt flow index of less than 15 g/10 min at 190.degree. C. under a weight of 2.16 kg.The novel polymer blends possess, inter alia, high rigidity, high impact strength and little tendency to undergo white fracture and are particularly suitable for the production of films and moldings.