Abstract: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Abstract: A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.

Abstract: An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.

Abstract: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Abstract: An apparatus for transmitting signals over a signal line includes a transmitter with an output connectable to the signal line, for a synchronization signal in a power saving mode and a wanted signal in a normal mode of operation, wherein the synchronization signal has a reduced amplitude as compared to an amplitude of the wanted signal and has a periodic data pattern so that the synchronization signal permits maintaining an alignment of the synchronization signal and a reference signal in the receiver.

Abstract: An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus switches to one of the first power saving mode and a second power saving mode, depending on the second signal at the reception interface and wherein the apparatus offers a first power consumption and a first wake-up time in the first power saving mode, and a second power consumption and a second wake-up time in the second power saving mode.

Abstract: A memory buffer comprises a first asynchronous latch chain interface connectable to at least one of a memory controller and a memory buffer, a second data interface connected to a memory device, and a circuit comprising a buffer and a processor, the circuit being coupled to the first and the second interfaces, so that data can be passed between the first interface and the buffer and between the second interface and the buffer and so that the processor is capable of processing at least one of the data from the first interface to the second interface and the data from the second interface according to a data processing functionality, wherein the data processing functionality of the processor is changeable by a programming signal received via an interface of a memory buffer.

Abstract: The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.

Abstract: A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.

Abstract: A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.

Abstract: Methods and apparatus for determining a temperature of a memory device. A memory device includes a memory array, a temperature configured to measure a temperature of the device and an evaluating circuit configured to receive a signal representative of the temperature measured by the temperature sensor and configured to generate a code word indicative of the measured temperature and a type of the temperature sensor, the temperature sensor being selected from one of at least two different temperature sensor types.

Abstract: Memory modules based on DDR-DRAMs are provided with a buffer and error checking module, which integrates an error data memory and a buffer/redriver functionality for conditioning data signals that are transferred to the memory module and output from the memory module and is suitable for the correction of user data stored erroneously in the DDR-DRAMs. The buffer and error checking module enables the integration of both error correction and buffer/redriver functionality on memory modules within the restricted memory module dimensions in accordance with definitive industry standards, simplified or improved routing of data lines and of control and address lines and also, by virtue of a reduction of erroneously transferred data to the data memory system, an increased real data transfer rate.

Abstract: Methods and apparatus for determining a temperature of a memory device. A memory device includes a memory array, a temperature configured to measure a temperature of the device and an evaluating circuit configured to receive a signal representative of the temperature measured by the temperature sensor and configured to generate a code word indicative of the measured temperature and a type of the temperature sensor, the temperature sensor being selected from one of at least two different temperature sensor types.

Abstract: An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performing a read access. The integrated semiconductor further includes a control circuit for controlling a write and read access. A temperature sensor for recording a chip temperature of the integrated semiconductor memory is connected to the control circuit. The control circuit is configured to generate a state of a third control signal at one of the first or at one of the second control terminals in a manner dependent on a temperature recorded by the temperature sensor.

Abstract: A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.

Abstract: Methods and apparatus for setting various terminations of a memory chip. In one embodiment, the memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.

Abstract: Methods and apparatus for allocating memory arrangement addresses to a buffer chip, during an initialization mode, for use in addressing one or more memory arrangements connected to the buffer chip are provided. A buffer circuit may receive first initialization data specifying a first set of available memory arrangement addresses and associate one or more of the first set of available memory arrangement addresses with the one or more memory arrangements connected to the buffer chip. The buffer circuit may also generate second initialization data specifying the set of available memory arrangement addresses available after the association. The second initialization data may be transmitted to another buffer circuit for use in address allocation or back to a memory access control unit.

Abstract: A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit.

Abstract: A method for transmitting a data stream from a circuit unit to a memory cell array includes receiving the data stream and demultiplexing it in response to a control signal, thereby dividing the data stream into a storage data stream and a mask data stream. The storage data stream is then buffered into a register unit, where it is divided into data stream components buffered in corresponding data register components on the basis of a clock signal and an address signal provided to the register unit. Meanwhile, the mask data stream is buffered in a mask register of the register unit. A composite data stream is then formed by combining selected data stream components in response to information provided by a data mask unit from the mask data stream buffered in the mask register. Data corresponding to this composite data stream is then provided to the memory cell array for storage therein.

Abstract: A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.