Patents by Inventor Gerald Deboy

Gerald Deboy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6667514
    Abstract: A semiconductor component includes a charge compensation structure wherein locations with a maximum local field strength are positioned in a compensation edge region of the charge compensation structure. Thus, an electrical parameter such as the on resistance of the semiconductor component can be substantially improved without influencing or impairing further parameters such as the breakdown voltage and the robustness with respect to TRAPATT oscillations. Methods of fabricating a semiconductor component with a charge compensation structure are also provided.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: December 23, 2003
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Gerald Deboy, Hans Weber, Armin Willmeroth
  • Publication number: 20030232477
    Abstract: A process for manufacturing of a semiconductor device comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode, the side of the zone of the second conductivity type facing the drain zone forming a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, areas of the first and second conductivity type nested in one another, comprises the step of:
    Type: Application
    Filed: June 6, 2003
    Publication date: December 18, 2003
    Inventors: Gerald Deboy, Dirk Ahlers, Helmut Strack, Michael Rueb, Hans Martin Weber
  • Patent number: 6664590
    Abstract: A circuit configuration for load-relieved switching has a bridge circuit with at least two controllable power switches, whose controlled paths are arranged in series with one another and between a first and a second supply potential. The circuit configuration has a drive circuit for driving the power switches, and an inductive element that is connected to output terminals of the bridge circuit. At least one power switch is designed as a field-effect-controllable, integrated transistor in accordance with the principle of charge carrier compensation or at least one power switch has deep pn junctions.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: December 16, 2003
    Assignee: Infineon Technologies AG
    Inventor: Gerald Deboy
  • Patent number: 6649459
    Abstract: The invention relates to a method for producing a semiconductor component including semiconductor areas of different conductivity types which are alternately positioned in a semiconductor body. The semiconductor areas of different conductivity types extend at least from one first zone to a position near a second zone. Because of variable doping in trenches and in the trench fillings, an electric field is generated which increases from both the first zone and the second zone.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: November 18, 2003
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Wolfgang Friza, Oliver Häberlen, Michael Rüb, Helmut Strack
  • Publication number: 20030209750
    Abstract: A semiconductor layer with laterally variable doping, and a method for producing it are disclosed. The trenches here are no longer filled up completely with doped semiconductor material. Instead, a doped balancing layer is deposited in a sense as a lining on the walls of the trenches. The doped balancing layer has a defined layer thickness that remains constant over an entire depth of the trenches. Furthermore, both a dopant concentration and the layer thickness of the balancing layer are adjusted such that a complete charge required for compensation is already contained in the balancing layer. The trenches here can advantageously have an arbitrarily great berm angle. The invention is especially advantageous in a peripheral region of semiconductor components with high depletion voltage strength.
    Type: Application
    Filed: June 2, 2003
    Publication date: November 13, 2003
    Applicant: Infineon Technologies AG
    Inventors: Gerald Deboy, Wolfgang Werner
  • Publication number: 20030205733
    Abstract: The semiconductor component is a charge carrier compensation component formed in a semiconductor body. A semiconductor basic body is disposed in the semiconductor body. The basic body has at least one compensation layer which adjoins a boundary layer and first regions of a first conductivity type and second regions of a second conductivity type are provided along a layout grid. A total quantity of charge of the first regions corresponds approximately to a total quantity of charge of the second regions. At least one semiconductor layer in the semiconductor body adjoins the semiconductor basic body at the boundary layer. A multiplicity of doped regions are embedded in the first surface of the semiconductor layer which form a grid for a cell array of the semiconductor component. The grid in the semiconductor layer is aligned independently of the layout grid in the semiconductor basic body.
    Type: Application
    Filed: May 12, 2003
    Publication date: November 6, 2003
    Applicant: Infineon Technologies AG
    Inventors: Gerald Deboy, Helmut Strack
  • Patent number: 6633064
    Abstract: The compensation component is formed with compensation regions in a semiconductor between two electrodes. By varying the second field and/or the first field, a location of a maximum field strength is displaced into the center of the compensation regions between the electrodes.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: October 14, 2003
    Assignee: Infineon Technologoes AG
    Inventors: Franz Auerbach, Gerald Deboy, Hans Weber
  • Patent number: 6630698
    Abstract: The invention relates to a high-voltage semiconductor component comprising semiconductor areas (4, 5) of alternating, different conductivity types which are arranged in a semiconductor body in an alternating manner.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: October 7, 2003
    Assignee: Infineon AG
    Inventors: Gerald Deboy, Dirk Ahlers, Helmut Strack, Michael Rueb, Hans Weber
  • Patent number: 6614090
    Abstract: The semiconductor component is a charge carrier compensation component formed in a semiconductor body. A semiconductor basic body is disposed in the semiconductor body. The basic body has at least one compensation layer which adjoins a boundary layer and first regions of a first conductivity type and second regions of a second conductivity type are provided along a layout grid. A total quantity of charge of the first regions corresponds approximately to a total quantity of charge of the second regions. At least one semiconductor layer in the semiconductor body adjoins the semiconductor basic body at the boundary layer. A multiplicity of doped regions are embedded in the first surface of the semiconductor layer which form a grid for a cell array of the semiconductor component. The grid in the semiconductor layer is aligned independently of the layout grid in the semiconductor basic body.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: September 2, 2003
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Helmut Strack
  • Patent number: 6607972
    Abstract: An edge termination is produced that is capable of handling high voltages. The edge termination is produced in a base material wafer that is produced in accordance with the principle of lateral charge compensation. The edge termination is formed in the base material wafer by implanting a rapidly diffusing dopant. Preferred dopants are selenium and sulfur. The high-voltage withstand strength is effected by a resulting doping profile which increases towards the edge termination.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: August 19, 2003
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Gerald Deboy
  • Patent number: 6577509
    Abstract: The invention relates to a semiconductor circuit having a drive circuit, a load that is disposed between a supply voltage, and a controllable, clocked semiconductor switching element for clocked switching of the load. The invention furthermore relates to a switch-mode power supply having such a semiconductor circuit.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: June 10, 2003
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Gerald Mündel, Harald Zöllinger
  • Publication number: 20030094857
    Abstract: A circuit configuration is used for off-load switching. The circuit configuration can be used as a component in a switch mode power supply, a clocked supply, a voltage regulator, and a lamp switch, wherein the circuit configuration is embodied as an IGBT, especially a field stop IGBT or alternately and additionally as a PT IGBT. A method for using the circuit configuration include three operating modes: in a first operating mode, power for a load is modulated by pulse modulation; in a second operating mode, the power is modulated by changing a switching-on time; and, in a third operating mode, both are implemented.
    Type: Application
    Filed: November 19, 2002
    Publication date: May 22, 2003
    Inventors: Gerald Deboy, Holger Huesken, Thomas Laska
  • Publication number: 20030025124
    Abstract: A circuit configuration for load-relieved switching has a bridge circuit with at least two controllable power switches, whose controlled paths are arranged in series with one another and between a first and a second supply potential. The circuit configuration has a drive circuit for driving the power switches, and an inductive element that is connected to output terminals of the bridge circuit. At least one power switch is designed as a field-effect controllable, integrated transistor in accordance with the principle of charge carrier compensation or at least one power switch has deep pn junctions.
    Type: Application
    Filed: August 1, 2002
    Publication date: February 6, 2003
    Inventor: Gerald Deboy
  • Publication number: 20030011039
    Abstract: A semiconductor component includes a charge compensation structure wherein locations with a maximum local field strength are positioned in a compensation edge region of the charge compensation structure. Thus, an electrical parameter such as the on resistance of the semiconductor component can be substantially improved without influencing or impairing further parameters such as the breakdown voltage and the robustness with respect to TRAPATT oscillations. Methods of fabricating a semiconductor component with a charge compensation structure are also provided.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 16, 2003
    Inventors: Dirk Ahlers, Gerald Deboy, Hans Weber, Armin Willmeroth
  • Patent number: 6504230
    Abstract: A compensating component and a method for the production thereof are described. Compensating regions are produced by implanting sulfur or selenium in a p-conductive semiconductor layer or, are provided as p-conductive regions, which are doped with indium, thallium and/or palladium, in a cluster-like manner inside an n-conductive region.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: January 7, 2003
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Hans-Joachim Schulze, Anton Mauder, Helmut Strack
  • Publication number: 20020167082
    Abstract: A semiconductor component, which functions according to the principle of charge carrier compensation, has incompletely ionized dopants that are additionally provided in a semiconductor body of the semiconductor component. When a reverse voltage is applied, the degree of compensation changes as a function of time and the breakdown voltage of the semiconductor component increases in a manner governed by the degree of compensation. The invention furthermore relates to a circuit configuration and to a method for doping a compensation layer according to the invention.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 14, 2002
    Inventors: Hans Weber, Dirk Ahlers, Gerald Deboy
  • Patent number: 6479876
    Abstract: The invention relates to a vertical power MOSFET having additional column-like zones (11, 12) which are arranged in an inner zone (1) and have the same and the opposite conductivity type as/to the inner zone (1). The charge carrier life is reduced in the additional zones (12), which are of the same conductivity type as the inner zone (1), and the inner zone (1) is dimensioned such that the space charge zone does not reach the junction between the inner zone and a drain zone.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: November 12, 2002
    Inventors: Gerald Deboy, Jenoe Tihanyi
  • Publication number: 20020159276
    Abstract: The invention relates to a semiconductor circuit having a drive circuit, a load that is disposed between a supply voltage, and a controllable, clocked semiconductor switching element for clocked switching of the load. The invention furthermore relates to a switch-mode power supply having such a semiconductor circuit.
    Type: Application
    Filed: February 21, 2002
    Publication date: October 31, 2002
    Inventors: Gerald Deboy, Gerald Mundel, Harald Zollinger
  • Patent number: 6465863
    Abstract: The invention relates to a power diode structure having improved dynamic characteristics which comprises a semiconductor body of a first conduction type. A semiconductor zone of the other conduction type which is contrary to the first conduction type is embedded in the one surface of said semiconductor body. The power diode also comprises an anode which contacts the semiconductor zone, and has a cathode which contacts the semiconductor body. At least one floating region of the second conduction type is provided in the semiconductor body.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 15, 2002
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Jens-Peer Stengl
  • Publication number: 20020123188
    Abstract: A compensating component and a method for the production thereof are described. Compensating regions are produced by implanting sulfur or selenium in a p-conductive semiconductor layer or, are provided as p-conductive regions, which are doped with indium, thallium and/or palladium, in a cluster-like manner inside an n-conductive region.
    Type: Application
    Filed: March 7, 2002
    Publication date: September 5, 2002
    Inventors: Gerald Deboy, Hans-Joachim Schulze, Anton Mauder, Helmut Strack