Patents by Inventor Gerald Ofner

Gerald Ofner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10301176
    Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel IP Corporation
    Inventors: Gerald Ofner, Thorsten Meyer, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin
  • Patent number: 10228725
    Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel IP Corporation
    Inventors: Sven Albers, Klaus Reingruber, Andreas Wolter, Georg Seidemann, Christian Geissler, Thorsten Meyer, Gerald Ofner
  • Patent number: 10211182
    Abstract: A package-on-package stacked microelectronic structure comprising a pair of microelectronic packages attached to one another in a flipped configuration. In one embodiment, the package-on-package stacked microelectronic structure may comprise a first and a second microelectronic package, each comprising a substrate having at least one package connection bond pad formed on a first surface of each microelectronic package substrate, and each having at least one microelectronic device electrically connected to the each microelectronic package substrate first surface, wherein the first and the second microelectronic package are connected to one another with at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: February 19, 2019
    Assignee: Intel IP Corporation
    Inventors: Thorsten Meyer, Gerald Ofner
  • Patent number: 10157869
    Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
  • Patent number: 10150668
    Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: December 11, 2018
    Assignee: Intel IP Corporation
    Inventors: Gerald Ofner, Thorsten Meyer, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin
  • Publication number: 20180286799
    Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Inventors: Thorsten MEYER, Gerald OFNER, Andreas WOLTER, Georg SEIDEMANN, Sven ALBERS, Christian GEISSLER
  • Publication number: 20180186627
    Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 5, 2018
    Inventors: Gerald Ofner, Thorsten Meyer, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin
  • Patent number: 9997444
    Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Gerald Ofner, Andreas Wolter, Georg Seidemann, Sven Albers, Christian Geissler
  • Publication number: 20180096966
    Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.
    Type: Application
    Filed: October 4, 2016
    Publication date: April 5, 2018
    Inventors: Thorsten Meyer, Gerald Ofner, Peter Scherl, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss
  • Publication number: 20180092443
    Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Sven Albers, Klaus Reingruber, Andreas Wolter, Georg Seidemann, Christian Geissler, Thorsten Meyer, Gerald Ofner
  • Publication number: 20180095426
    Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Sven Albers, Klaus Reingruber, Andreas Wolter, Georg Seidemann, Christian Geissler, Thorsten Meyer, Gerald Ofner
  • Patent number: 9888577
    Abstract: Passive electrical devices are described with a polymer carrier. In one example, a conductive layer is formed over a polymer substrate in a pattern to form a passive electrical device and at least two terminals of the device. A plurality of external connection pads are connected to the terminals of the device.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: February 6, 2018
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Gerald Ofner, Sven Albers, Reinhard Mahnkopf
  • Patent number: 9856136
    Abstract: A chip arrangement may include: a mold compound; and a microelectromechanical systems device at least partially embedded in the mold compound.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: January 2, 2018
    Assignee: Intel Deutschland GmbH
    Inventors: Thorsten Meyer, Gerald Ofner, Christian Mueller, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin
  • Publication number: 20170317016
    Abstract: A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 2, 2017
    Inventors: Alexander HEINRICH, Bernd GOLLER, Thorsten MEYER, Gerald OFNER
  • Publication number: 20170217766
    Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 11, 2017
    Publication date: August 3, 2017
    Inventors: Gerald Ofner, Thorsten Meyer, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin
  • Publication number: 20170178993
    Abstract: An electronic component which comprises an electrically insulating layer having at least one through hole, a patterned electrically conductive structure at least partially on the electrically insulating layer, an electronic chip electrically coupled with the patterned electrically conductive structure, an encapsulant at least partially encapsulating the electronic chip, and at least one electrically conductive contact structure at least partially in the at least one through hole in contact with at least part of the patterned electrically conductive structure.
    Type: Application
    Filed: December 18, 2016
    Publication date: June 22, 2017
    Inventors: Thorsten MEYER, Edward Fuergut, Gerald Ofner, Petteri Palm
  • Patent number: 9663353
    Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 30, 2017
    Assignee: INTEL IP CORPORATION
    Inventors: Gerald Ofner, Thorsten Meyer, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin
  • Publication number: 20170103956
    Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 13, 2017
    Inventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
  • Patent number: 9550670
    Abstract: Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: January 24, 2017
    Assignee: INTEL IP CORPORATION
    Inventors: Christian Geissler, Thorsten Meyer, Gerald Ofner, Reinhard Mahnkopf, Andreas Augustin, Christian Mueller
  • Patent number: 9543224
    Abstract: Semiconductor packages and methods, systems, and apparatuses of forming such packages are described. A method of forming a semiconductor package may include encapsulating a semiconductor die with a molding compound, applying a seed layer on the die and the molding compound, applying a resist layer on the seed layer, exposing a first portion of the resist layer, and exposing a second portion of the resist layer. The first portion can include a first area of the resist layer to be used for forming a redistribution layer (RDL) without including a second area of the resist layer to be used for forming an electrical communications pathway between at least one of the contact pads and the RDL. The second portion can include the second area of the resist layer that includes the electrical communications pathway.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 10, 2017
    Assignee: Intel IP Corporation
    Inventors: Thorsten Meyer, Gerald Ofner, Robert L. Sankman