Abstract: A molded power semiconductor package includes power semiconductor dies embedded in a mold compound and a lead frame embedded in the mold compound above the power semiconductor dies. A first part of the lead frame includes branches electrically connected to a first load terminal of the power semiconductor dies. A second part of the lead frame is spaced inward from the branches of the first part, and electrically connected to a gate terminal of the power semiconductor dies. The first part of the lead frame has a protrusion that juts out from a first side face of the mold compound to form a first lead of the molded package. A longitudinal axis of the second part of the lead frame intersects the first lead. The second part of the lead frame is physically disconnected from the first lead by a severed region of the lead frame.

Abstract: A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.

Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.

Abstract: A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.

Abstract: Disclosed herein are integrated circuit (IC) packages, and related structures and techniques. In some embodiments, an IC package may include: a die; a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects and solder; a solder resist; and second-level interconnects coupled to the redistribution structure through openings in the solder resist.

Abstract: A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.

Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

Abstract: Disclosed herein are integrated circuit (IC) packages, and related structures and techniques. In some embodiments, an IC package may include: a die; a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects and solder; a solder resist; and second-level interconnects coupled to the redistribution structure through openings in the solder resist.

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.

Abstract: A package-on-package stacked microelectronic structure comprising a pair of microelectronic packages attached to one another in a flipped configuration. In one embodiment, the package-on-package stacked microelectronic structure may comprise a first and a second microelectronic package, each comprising a substrate having at least one package connection bond pad formed on a first surface of each microelectronic package substrate, and each having at least one microelectronic device electrically connected to the each microelectronic package substrate first surface, wherein the first and the second microelectronic package are connected to one another with at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.

Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.

Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.